The equivalent circuit of each LVDS output buffer is shown in Figure 7-4. After reset, the buffer presents an output impedance of 100Ω to match with the external 100Ω termination.

NOTE: Default swing across 100Ω load is ±350mV. Use the LVDS SWING bits to change the swing.

Figure 7-4 LVDS Buffer Equivalent Circuit

The V_DIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination. The V_DIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.

Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination, as shown in Figure 7-5. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively.

The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity.

Figure 7-5 LVDS Buffer Differential Termination