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ZHCSCA6B April 2014 – October 2020 ADS4245-EP

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6.7 Digital Characteristics

At AVDD = 1.8V and DRVDD = 1.8V (unless otherwise noted). DC specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level '0' or '1'.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)⁽¹⁾
High-level input voltage		All digital inputs support 1.8V and 3.3V CMOS logic levels	1.3			V
Low-level input voltage		All digital inputs support 1.8V and 3.3V CMOS logic levels			0.4	V
High-level input current	SDATA, SCLK⁽²⁾	V_HIGH = 1.8V		10		µA
High-level input current	SEN⁽³⁾	V_HIGH = 1.8V		0		µA
Low-level input current	SDATA, SCLK	V_LOW = 0V		0		µA
Low-level input current	SEN	V_LOW = 0V		10		µA
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
High-level output voltage			DRVDD – 0.1	DRVDD		V
Low-level output voltage				0	0.1	V
Output capacitance (internal to device)						pF
DIGITAL OUTPUTS, LVDS INTERFACE
High-level output differential voltage	V_ODH	With an external 100Ω termination	220	350	490	mV
Low-level output differential voltage	V_ODL	With an external 100Ω termination	–490	–350	–220	mV
Output common-mode voltage	V_OCM		0.9	1.05	1.25	V

(1) SCLK, SDATA, and SEN function as digital input terminals in serial configuration mode.

(2) SDATA, SCLK have internal 150kΩ pull-down resistor.

(3) SEN has an internal 150kΩ pull-up resistor to AVDD. Because the pull-up is weak, SEN can also be driven by 1.8V or 3.3V CMOS buffers.

With external 100Ω termination.

Figure 6-1 LVDS Output Voltage Levels

See datasheet for absolute maximum and minimum recommended operating conditions.

Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).

Enhanced plastic product disclaimer applies.

Figure 6-2 ADS4245-EP Electromigration Fail Mode Chart

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6.7 Digital Characteristics