ZHCS114E march 2011 – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246
PRODUCTION DATA
Example design requirements are listed in Table 9-1 for the ADC portion of the signal chain. These do not necessarily reflect the requirements of an actual system, but rather demonstrate why the ADS4246 may be chosen for a system based on a set of requirements.
| Design Parameter | Example Design Requirement | ADS4246 CAPABILITY |
|---|---|---|
| Sampling rate | ≥ 122.88 Msps to allow 80 MHz of unaliased bandwidth | Max sampling rate: 160 Msps |
| Input frequency | > 125 MHz to accommodate full 2nd nyquist zone | Large signal –3 dB bandwidth: 400-MHz operation |
| SNR | > 68 dBFS at –1 dFBS, 170 MHz | 70.4 dBFS at –1 dBFS, 170 MHz |
| SDFR | > 77 dBc at –1 dFBS, 170 MHz | 82 dBc at –1 dBFS, 170 MHz |
| Input full scale voltage | 2 Vpp | 2 Vpp |
| Overload recovery time | < 3 clock cycles | 1 clock cycle |
| Digital interface | DDR LVDS | DDR LVDS |
| Power consumption | <200 mW per channel | 166 mW per channel |