The equivalent circuit of each LVDS output buffer is shown in Figure 8-22. After reset, the buffer presents an output impedance of 100 Ω to match with the external 100-Ω termination.

Default swing across 100-Ω load is ±350 mV. Use the LVDS SWING bits to change the swing.

Figure 8-22 LVDS Buffer Equivalent Circuit

The V_DIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The V_DIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.

Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination, as shown in Figure 8-23. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively.

The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, it helps to improve signal integrity.

Figure 8-23 LVDS Buffer Differential Termination