The ADS42xx should be driven by a high performance clock driver such as a clock jitter cleaner. The clock needs to have low noise to maintain optimal performance. LVPECL is the most common clocking interface, but LVDS and LVCMOS can be used as well. It is not advised to drive the clock input from an FPGA unless the noise degradation can be tolerated, such as for input signals near DC where the clock noise impact is minimal.