9.1.2.1 Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This operation improves the common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each input pin is recommended to damp out ringing caused by package parasitics.

SFDR performance can be limited as a result of several reasons, including the effects of sampling glitches; nonlinearity of the sampling circuit; and nonlinearity of the quantizer that follows the sampling circuit. Depending on the input frequency, sample rate, and input amplitude, one of these factors generally plays a dominant part in limiting performance. At very high input frequencies (greater than approximately 300 MHz), SFDR is determined largely by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity usually limits performance.

Glitches are caused by the opening and closing of the sampling switches. The driving circuit must present a low source impedance to absorb these glitches. Otherwise, glitches could limit performance, primarily at low input frequencies (up to approximately 200 MHz). Low impedance (less than 50 Ω) must be presented for the common-mode switching currents. This configuration can be achieved by using two resistors from each input terminated to the common-mode voltage (VCM pin).

The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the sampling glitches inside the device itself. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff frequency (larger C) absorbs glitches better but reduces the input bandwidth. On the other hand, with a higher cutoff frequency (smaller C), bandwidth support is maximized. However, the sampling glitches must then be supplied by the external drive circuit. This tradeoff has limitations as a result of the presence of the package bond-wire inductance.

In the ADS4249, the R-C component values have been optimized when supporting high input bandwidth (up to 550 MHz). However, in applications with input frequencies up to 200 MHz to 300 MHz, the filtering of the glitches can be improved further using an external R-C-R filter; see Figure 74 and Figure 75.

In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. Furthermore, the ADC input impedance must be considered. Figure 72 and Figure 73 show the impedance (Z_IN = R_IN || C_IN) looking into the ADC input pins.

Figure 72. ADC Analog Input Resistance (R_IN) Across Frequency

Figure 73. ADC Analog Input Capacitance (C_IN) Across Frequency

9.1.2.2 Driving Circuit

Three example driving circuit configurations are shown in Figure 74, Figure 75, and Figure 76. They are optimized for low bandwidth (low input frequencies), high bandwidth (higher input frequencies), and very high bandwidth (very high input frequencies), respectively. Note that three of the drive circuits have been terminated by 50 Ω near the ADC side. The termination is accomplished by a 25-Ω resistor from each input to the 0.95-V common-mode (VCM) from the device. This architecture allows the analog inputs to be biased around the required common-mode voltage.

The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch; good performance is obtained for high-frequency input signals. For example, ADT1-1WT transformers can be used for the first two configurations (Figure 74 and Figure 75) ADTL2-18 transformers can be used for the third configuration (Figure 76). An optional termination resistor pair may be required between the two transformers, as shown in Figure 74, Figure 75, and Figure 76. The center point of this termination is connected to ground to improve the balance between the P and M sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (in the case of 50-Ω source impedance).

Figure 74. Drive Circuit with Low Bandwidth (for Low Input Frequencies Less Than 150 MHz)

Figure 75. Drive Circuit with High Bandwidth
(for High Input Frequencies Greater Than 150 MHz and Less Than 270 MHz)

Figure 76. Drive Circuit with Very High Bandwidth (Greater than 270 MHz)

All of these examples show 1:1 transformers being used with a 50-Ω source. As explained in the Drive Circuit Requirements section, this configuration helps to present a low source impedance to absorb the sampling glitches. With a 1:4 transformer, the source impedance is 200 Ω. The higher source impedance is unable to absorb the sampling glitches effectively and can lead to degradation in performance (compared to using 1:1 transformers).

In almost all cases, either a band-pass or low-pass filter is required to obtain the desired dynamic performance, as shown in Figure 77. Such filters present low source impedance at the high frequencies corresponding to the sampling glitch and help avoid performance losses associated with the high source impedance.

Figure 77. Drive Circuit with a 1:4 Transformer

Table 11. Example Design Requirements for ADS4249

9.2.2.1 Analog Input

The analog inputs of the ADS4249 are typically driven by a fully differential amplifier. The amplifier must have sufficient bandwidth for the frequencies of interest. The noise and distortion performance of the amplifier affect the combined performance of the ADC and amplifier. The amplifier is often ac coupled to the ADC to allow both the amplifier and ADC to operate at the optimal common mode voltages. The amplifier can be dc-coupled to the ADC if required. An alternate approach is to drive the ADC using transformers. DC coupling cannot be used with the transformer approach.

9.2.2.2 Common Mode Voltage Output (VCM)

The common mode voltage output is shared between both ADC channels. To maintain optimal isolation, an LC filter may need to be placed on the VCM node between the channels (not shown in schematic). At a minimum, place a bypass capacitor on the node that has sufficiently low impedance at the desired operating frequencies. Note the VCM pin maximum output current in the electrical tables when using VCM in alternate ways.

9.2.2.3 Clock Driver

The ADS4249 supports both LVDS and CMOS interfaces. The LVDS interface must be used for best performance when operating at maximum sampling rate. The LVDS outputs can be connected directly to the FPGA without any additional components. When using CMOS outputs, place resistors in series with the outputs to reduce the output current spikes to limit the performance degradation. The resistors must be large enough to limit current spikes but not so large as to significantly distort the digital output waveform. Use an external CMOS buffer when driving distances greater than a few inches to reduce ground bounce within the ADC.

9.2.2.4 Digital Interface

The ADS4249 supports both LVDS and CMOS interfaces. Use the LVDS interface for best performance when operating at maximum sampling rate. The LVDS outputs can be connected directly to the FPGA without any additional components. When using CMOS outputs, place resistors in series with the outputs to reduce the output current spikes to limit the performance degradation. The resistors must be large enough to limit current spikes but not so large as to significantly distort the digital output waveform. Use an external CMOS buffer when driving distances greater than a few inches to reduce ground bounce within the ADC.