米6体育平台手机版

ZHCS367E July 2011 – January 2016 ADS4249

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RGC|64
- MPQF125F

散热焊盘机械数据 (封装 | 引脚)

RGC|64
- QFND123N

订购信息

11 Layout

11.1 Layout Guidelines

11.1.1 Grounding

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. See the ADS4226 Evaluation Module (SLAU333) for details on layout and grounding.

11.1.2 Exposed Pad

In addition to providing a path for heat dissipation, the PowerPAD is also electrically connected internally to the digital ground. Therefore, the exposed pad must be soldered to the ground plane for best thermal and electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON PCB Attachment (SLUA271).

11.1.3 Routing Analog Inputs

Routing differential analog input pairs (INP_x and INM_x) close to each other is advisable. To minimize the possibility of coupling from a channel analog input to the sampling clock, the analog input pairs of both channels must be routed perpendicular to the sampling clock; see the ADS4226 Evaluation Module (SLAU333) for reference routing. Figure 85 illustrates a snapshot of the PCB layout from the ADS42xxEVM.

11.1.4 Routing Digital Inputs

The digital outputs must be routed away from the analog inputs and any noise sensitive circuits. Avoid routing the digital outputs in parallel to any analog trace. The digital outputs must be routed over a solid ground plane all the way to the FPGA. Keep the digital traces as short as possible to reduce EMI emissions. The traces must be matched length to maintain timing, however mismatches in the trace lengths can be taken into account by including the delay differences in the FPGA timing constraints.

11.2 Layout Example

Figure 85. ADS42xxEVM PCB Layout