11.1 Layout Guidelines

• The length of the positive and negative traces of a differential pair should be matched to within 2 mils (0.051mm) of each other.
• Each differential pair length should be matched within 10 mils (0.254 mm) of each other.
• When the ADC is used on the same PCB with a digital intensive component such as FPGA or ASIC, separate digital and analog ground planes should be used. These separate ground planes should not overlap to minimize undesired coupling.
• Connect decoupling caps directly to ground and place close to the ADC power pins and the power supply pins to filter high-frequency current transients directly to the ground plane. This is illustrated in Figure 90.

• Ground and power planes should be wide enough to keep the impedance very low. In a multi-layer PCB, one layer each should be dedicated to ground and power planes.
• All high speed serdes traces should be routed straight with minimum curves and bends. Where a bend is necessary, avoid making very sharp right angle bends in the trace.
• FR4 material may be used for the PCB core dielectric up to the maximum 3.125-Gbps bit rate supported by ADS42JBxx device family. Path loss can be compensated for by adjusting the drive strength from the ADS42JBxx using SPI register 0x36.

Figure 90. Recommended Placement of Power Supply De-coupling Capacitors

11.2 Layout Example

Figure 91. Layout Recommendation