12.1 Layout Guidelines

• The length of the positive and negative traces of a differential pair must be matched to within 2 mils of each other.
• Each differential pair length must be matched within 10 mils of each other.
• When the ADC is used on the same printed circuit board (PCB) with a digital intensive component (such as an FPGA or ASIC), separate digital and analog ground planes must be used. Do not overlap these separate ground planes to minimize undesired coupling.
• Connect decoupling capacitors directly to ground and place these capacitors close to the ADC power pins and the power-supply pins to filter high-frequency current transients directly to the ground plane, as shown in Figure 125.
Figure 125. Recommended Placement of Power-Supply Decoupling Capacitors
• Ground and power planes must be wide enough to keep the impedance very low. In a multilayer PCB, one layer each must be dedicated to ground and power planes.
• All high-speed SERDES traces must be routed straight with minimum bends. Where a bend is necessary, avoid making very sharp right angle bends in the trace.
• FR4 material can be used for the PCB core dielectric, up to the maximum 3.125 Gbps bit rate supported by the ADS42JBx9 device family. Path loss can be compensated for by adjusting the drive strength from the device using SPI register 36h.

12.2 Layout Example

Figure 126. ADS42JBx9 EVM Top Layer