11.1 Layout Guidelines

• The length of the positive and negative traces of a differential pair must be matched to within 2 mils of each other.
• Each differential pair length must be matched within 10 mils of each other.
• When the ADC is used on the same printed circuit board (PCB) with a digital intensive component [such as a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC)], use separate digital and analog ground planes to minimize undesired coupling. Note that these ground planes must not overlap.
• Connect decoupling capacitors directly to ground and place these capacitors close to the ADC power pins and the power-supply pins to filter high-frequency current transients directly to the ground plane, as illustrated in Figure 126.
• Ground and power planes must be wide enough to keep the impedance very low. In a multilayer PCB, dedicate one layer to ground and another to power planes.

Figure 126. Recommended Placement of Power-Supply Decoupling Capacitors

11.2 Layout Example

Figure 127. Example Layout

Figure 128. Example PCB Layer Stack