8.3.1 Digital Processing Blocks

The ADS5263 integrates a set of commonly useful digital functions that can be used to ease system design. These functions are shown in the digital block diagram of Figure 45 and described in the following sections.

Figure 45. Block Diagram – Digital Processing

8.3.2 Digital Gain

ADS5263 includes programmable digital gain settings from 0 dB to 12 dB in steps of 1 dB. The benefit of digital gain is to get improved SFDR performance. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades by about 1 dB. So, the gain can be used to trade off between SFDR and SNR.

For each gain setting, the analog supported input full-scale range scales proportionally, as shown in Table 1. The full-scale range depends on the ADC mode used (16-bit or 14-bit).

After a reset, the device comes up in the 0-dB gain mode. To use other gain settings, program the <GAIN CH x> register bits.

8.3.3 Digital Filter

The digital processing block includes the option to filter and decimate the ADC data outputs digitally. Various filters and decimation rates are supported – decimation rates of 2, 4, and 8 and low-pass, high-pass, and band-pass filters are available. The filters are internally implemented as a 24-tap asymmetric FIR (even-tap) using pre-defined coefficients following the equation which is described in Figure 46.

Alternatively, some of the filters can be configured as a 23-tap asymmetric FIR (or odd-tap filters) following the equation which is described in Figure 47.

Figure 46. 24-tap Filter Equation

Figure 47. 23-tap Filter Equation

In the equations,

h0, h1 …h11 are 12-bit signed 2s complement representation of the coefficients (-2048 to +2047)

x(n) is the input data sequence to the filter

y(n) is the filter output sequence

Details of the registers used for configuring the digital filters are show in Table 2 and Table 3.

See Table 3 for choosing the right combination of decimation rate and filter types.

Figure 48. Filter Response – Decimate by 2

Figure 49. Filter Response – Decimate by 4

8.3.4 Custom Filter Coefficients

In addition to these built-in filters, customers also have the option of using their own custom 12-bit signed coefficients. Only 12 coefficients can be specified according to Figure 48 or Figure 49. These coefficients (h0 to h11) must be configured in the custom coefficient registers as:

Register content = 12-bit signed representation of [real coefficient value × 2¹¹]

The 12 custom coefficients must be loaded into 12 separate registers for each channel (refer Table 4 ). The MSB bit of each coefficient register decides if the built in filters or custom filters are used. If the MSB bit <EN CUSTOM FILT> is reset to 0, then built in filter coefficients are used. Else, the custom coefficients are used.

8.3.4.1 Custom Filter Without Decimation

Another mode exists to use the digital filter without decimation. In this mode, the filter behaves like a 12-tap symmetric FIR filter as per the equation described by Figure 50

Figure 50. 12-tap Symmetric Filter Equation

Where,

h6, h7 …h11 are 12-bit signed 2s complement representation of the coefficients (-2048 to +2047)

x(n) is the input data sequence to the filter

y(n) is the filter output sequence

In this mode, as the filter is implemented as a 12-tap symmetric FIR, only 6 custom coefficients need to be specified and must be loaded in registers h6 to h11. Table 4

To enable this mode, use the register setting specified in the last row of Table 3

8.3.5 Digital Averaging

The ADS5263 includes an averaging function where the ADC digital data from two (or four) channels can be averaged. The averaged data is output on specific LVDS channels. Table 5 shows the combinations of the input channels that can be averaged and the LVDS channels on which averaged data is available

8.3.6 Performance with Digital Processing Blocks

The ADS5263 provides very high SNR along with high sampling rates. In applications where even higher SNR performance is desired, digital processing blocks such as averaging and decimation filters can be used advantageously to achieve this. Table 6 shows the improvement in SNR that can be achieved compared to the default value, using these modes.

8.3.7 Flexible Mapping o Channel Data to LVDS Outputs

ADS5263 has a mapping function by the use of which the digital data for any channel can be routed to any LVDS output. So, as an example, in the 1-wire interface, the channel-1 ADC output can be output either on OUT1 pins or on OUT2 or OUT3 or OUT4 pins.

This flexibility in mapping simplifies board designs by avoiding complex routing that would be caused by a rigid mapping of input channels and output pins. This can also lead to potential saving in PCB layers and hence cost. The mapping is programmable using the register bits <MAP_Ch1234_OUTn> as shown in Figure 51 and Figure 52.

Figure 51. Mapping in 2-Wire Interface

Figure 52. Mapping in 1-Wire Interface

8.3.8 Output LVDS Interface

The ADS5263 offers several flexible output options, making it easy to interface to an ASIC or an FPGA. Each of these options can be easily programmed using the serial interface. A summary of all the options is presented in Table 7, along with the default values after power up and reset. Following this, each option is described in detail.

The output interface options are:

1. 1-wire, 16× serialization with DDR bit clock and 1× frame clock
   • The 16-bit ADC data is serialized and output over one LVDS pair per channel together with an 8× bit clock and 1× frame clock. The output data rate is 16× sample rate; hence, it is suited for low sample rates, typically up to 50 MSPS.
2. 2-wire, 8× serialization with DDR bit clock and 0.5× frame clock (16 bit ADC mode, Figure 54 and Figure 55)
   • Here, the 16 bit ADC data is serialized and output over two LVDS pairs per channel. The output data rate is 8x sample rate, with a 4x bit clock and 0.5x frame clock.
     Because the output data rate is half compared to the 1-wire case, this interface can be used up to the maximum sample rate of the device.
3. 2-wire, 8× serialization with DDR bit clock and 0.5× frame clock (14-bit ADC mode)
   • Here, the 14-bit ADC data is padded with two zero bits. The combined 16-bit data is then serialized and output over two LVDS pairs per channel. The output data rate is 8× sample rate, with a 4× bit clock and 0.5× frame clock Because the output data rate is half compared to the 1-wire case, this interface can be used up to the maximum sample rate of the device.
4. 1-wire, 14× serialization with DDR bit clock and 1× frame clock (14-bit ADC mode)
   • The 14-bit ADC data is serialized and output over one LVDS pair per channel together with a 7× bit clock and 1× frame clock. The output data rate is 14× sample rate; hence, it is suited for low sample rates, typically up to 50 MSPS.
5. 2-wire, 7× serialization with DDR bit clock and 0.5× frame clock (14-bit ADC mode, Figure 57 and Figure 58)
   • Here, the 14-bit ADC data is serialized and output over two LVDS pairs per channel. The output data rate is 7× sample rate, with a 3.5× bit clock and 0.5× frame clock. Because the output data rate is half compared to the 1-wire case, this interface can be used up to the maximum sample rate of the device.
6. 1-wire, 18× serialization with DDR bit clock and 1× frame clock – Here, the 18-bit data from the digital processing block is serialized and output over one LVDS pair per channel, together with a 9× bit clock and 1x frame clock. The output data rate is 18× sample rate; hence, it is suited for low sample rates, typically up to 40 MSPS. This interface is primarily intended to be used when the averaging and digital filters are enabled.

Figure 53. Output LVDS Interface, 1-Wire, 16× Serialization

Figure 54. LVDS Output Interface, 2-Wire, 8× Serialization, Bytewise and Bitwise Modes

Figure 55. LVDS Output Interface, 2-Wire, 8× Serialization, Wordwise Mode

Figure 56. LVDS Output Interface, 1-Wire, 18× Serialization

Figure 57. LVDS Output Interface, 1-Wire, 14× Serialization

Figure 58. LVDS Output Interface, 2-Wire, 7× Serialization

8.3.9 Programmable LCLK Phase

The ADS5263 allows programmability of the edge of the output bit clock (LCLK) using register bits <PHASE_DDR> as follows:

The default value of PHASE_DDR after reset is 10, and the default phase corresponds to Figure 59.

Figure 59. Default LCLK Phase

The phase can also be changed to one of the following states by changing the value of the <PHASE_DDR1:0> bits (and setting register bit EN_REG_42 = 1).

Figure 60. Programmable LCLK Phases

8.4.1 Device Configuration

ADS5263 has several modes that can be configured using a serial programming interface, as described below. In addition, the device has dedicated parallel pins for controlling common functions such as power down and internal or external reference selection.

8.4.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back on SDOUT pin. This may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC.

By default, after power up and device reset, the SDOUT pin is in the high-impedance state. When the readout mode is enabled using the register bit <READOUT>, SDOUT outputs the contents of the selected register serially, described as follows.

• Set register bit <READOUT> = 1 to put the device in serial readout mode. This disables any further writes into the internal registers, EXCEPT the register at address 1. Note that the <READOUT> bit itself is also located in register 1.
  The device can exit readout mode by writing <READOUT> to 0.
  Only the contents of register at address 1 cannot be read in the register readout mode.
• Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content is to be read.
• The device serially outputs the contents (D15–D0) of the selected register on the SDOUT pin.
• The external controller can latch the contents at the rising edge of SCLK.
• To exit the serial readout mode, reset register bit <READOUT> = 0, which enables writes into all registers of the device. At this point, the SDOUT pin enters the high-impedance state.

Figure 61. Serial Readout Timing

8.5.1 Serial Interface

The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins CS (serial interface enable), SCLK (serial interface clock) and SDATA (serial interface data).

When CS is low,

• Serial shift of bits into the device is enabled.
• Serial data (on SDATA pin) is latched at every rising edge of SCLK.
• The serial data is loaded into the register at every 24^th SCLK rising edge.

In case the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active CS pulse.

The first 8 bits form the register address and the remaining 16 bits form the register data. The interface can work with SCLK frequencies from 20 MHz down to very low speeds (a few hertz) and also with non-50% SCLK duty cycle.

8.5.2 Register Initialization

After power up, the internal registers MUST be initialized to their default values. This can be done in one of two ways:

1. Through a hardware reset by applying a low-going pulse on the RESET pin (of width greater than 10 ns) as shown in Figure 62.

OR

2. By applying software reset. Using the serial interface, set the <RESET> bit (D7 in register 0x00) to HIGH. This initializes internal registers to their default values and then self-resets the <RESET> bit to low. In this case, the RESET pin is kept high (inactive).

Figure 62. Serial Interface Timing

Table 10. Summary of Functions Supported by Serial Interface⁽¹⁾

8.6.1 Default State After Reset

• Device is in normal operation mode with 16-bit ADC enabled for all 4 channels.
• Output interface is 1-wire, 16× serialization with 8× bit clock and 1× frame clock frequency
• Serial readout is disabled
• PD pin is configured as global power-down pin
• LVDS output current is set to 3.5 mA; internal termination is disabled.
• Digital gain is set to 0 dB.
• Digital modes such as LFNS, digital filters are disabled.

8.6.2 Description of Serial Registers