8.3.2 Input Multiplexer and Sampler

The input multiplexer determines the mapping of the input pins (IN1 to IN32) to the inputs that are sampled and converted by the ADCs (ADC1 to ADC16). Each ADC has two sets of sampling circuits (termed odd and even) and alternately converts the inputs presented to them.

The sampling windows for the odd and even sampling circuits of each ADC are derived from the system clock. A pair of ADCs are used in Figure 57, Figure 58, and Figure 59 to illustrate how the odd and even sampling phases are derived for each ADC in each input mode. AIN1 (t₁) refers to the AIN1 input sampled at the t₁ instant. ADC1o refers to the odd sample converted by ADC1 and ADC1e refers to the even sample converted by ADC1. The input sampling and conversion schemes for the 32-, 16-, and 8-input modes are illustrated in Figure 57, Figure 58, and Figure 59, respectively.

Figure 57. Input Sampling and Conversion Scheme (32-Input Mode)

Figure 58. Input Sampling and Conversion Scheme (16-Input Mode)

Figure 59. Input Sampling and Conversion Scheme (8-Input Mode)

Mapping the inputs of the odd and even sampling circuits of subsequent-numbered ADCs to subsequent-numbered sets of input pairs repeats in a similar manner.

The sampling rate (f_SAMP) can be defined as the rate at which the device converts each analog input presented to it. The relationship between the sampling rate and the system clock frequency is listed in Table 2 for the three input modes.

In 16-input mode, each ADC converts one input at a sampling rate equal to the system clock. In 32-input mode, one ADC alternately converts two sets of inputs, each at a sampling rate that is half the system clock. In the 8-input mode, two ADCs convert the same input in interleaved manner.

In 16-input mode, a ping-pong operation exists between two sampling circuits of one ADC that are sampling the same input. The mismatch between the two sampling circuit bandwidths can result in an interleaving spur at
(f_S / 2 ± f_IN), where f_S is the frequency of the system clock and f_IN is the frequency of the input signal.

In 8-input mode, additional interleaving across two adjacent ADCs is present in addition to the ping-pong operation between the two sampling circuits of the same ADC. This increased mismatch can result in significant interleaving spurs at (f_S / 2 ± f_IN) and (f_S / 4 ± f_IN). The offset mismatch between the four sets of sampling circuits can result in a spur at f_S / 4.

For the 32-input mode, the sampling instants of the even-numbered input signals are offset from the sampling instants of the odd-numbered input signals by one system clock period. The magnitude of the interleaving spurs increases when the input frequency is increased because the sampling bandwidth mismatch across the different sampling circuits results in larger phase error mismatches when the input frequency is increased.