米6体育平台手机版

ZHCSDS3C May 2015 – April 2018 ADS52J90

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

ZZE|198

散热焊盘机械数据 (封装 | 引脚)

订购信息

6 Pin Configuration and Functions

ZZE Package

NFBGA-198 (15 mm × 9 mm)

Top View

Pin Functions⁽²⁾

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
AVDD_1P8	A4, E6, F6, G5, G6, M5, M6, N6, P6, V4	P	1.8-V analog supply voltage
AVSS	B4, C4, D4, H5, H6, J5, J6, K5, K6, L5, L6, R4, R5, T4, T5, U4, U6, V6	G	Analog ground
CLKM	U5	I	Differential clock input pins. A single-ended clock is also supported. See the Clock Input section for further details.
CLKP	V5	I
CML1_OUTM	A10	O	JESD output lane 1
CML1_OUTP	A9	O	JESD output lane 1
CML2_OUTM	B11	O	JESD output lane 2
CML2_OUTP	A11	O	JESD output lane 2
CML3_OUTM	D11	O	JESD output lane 3
CML3_OUTP	C11	O	JESD output lane 3
CML4_OUTM	F11	O	JESD output lane 4
CML4_OUTP	E11	O	JESD output lane 4
CML5_OUTM	V10	O	JESD output lane 5
CML5_OUTP	V9	O	JESD output lane 5
CML6_OUTM	U11	O	JESD output lane 6
CML6_OUTP	V11	O	JESD output lane 6
CML7_OUTM	R11	O	JESD output lane 7
CML7_OUTP	T11	O	JESD output lane 7
CML8_OUTM	N11	O	JESD output lane 8
CML8_OUTP	P11	O	JESD output lane 8
DCLKM	K11	O	LVDS bit clock output
DCLKP	J11	O	LVDS bit clock output
DOUTM1	B10	O	LVDS data lane 1
DOUTP1	B9	O	LVDS data lane 1
DOUTM2	C10	O	LVDS data lane 2
DOUTP2	C9	O	LVDS data lane 2
DOUTM3	D10	O	LVDS data lane 3
DOUTP3	D9	O	LVDS data lane 3
DOUTM4	E10	O	LVDS data lane 4
DOUTP4	E9	O	LVDS data lane 4
DOUTM5	F10	O	LVDS data lane 5
DOUTP5	F9	O	LVDS data lane 5
DOUTM6	G10	O	LVDS data lane 6
DOUTP6	G9	O	LVDS data lane 6
DOUTM7	H10	O	LVDS data lane 7
DOUTP7	H9	O	LVDS data lane 7
DOUTM8	G11	O	LVDS data lane 8
DOUTP8	H11	O	LVDS data lane 8
DOUTM9	M11	O	LVDS data lane 9
DOUTP9	L11	O	LVDS data lane 9
DOUTM10	L10	O	LVDS data lane 10
DOUTP10	L9	O	LVDS data lane 10
DOUTM11	M10	O	LVDS data lane 11
DOUTP11	M9	O	LVDS data lane 11
DOUTM12	N10	O	LVDS data lane 12
DOUTP12	N9	O	LVDS data lane 12
DOUTM13	P10	O	LVDS data lane 13
DOUTP13	P9	O	LVDS data lane 13
DOUTM14	R10	O	LVDS data lane 14
DOUTP14	R9	O	LVDS data lane 14
DOUTM15	T10	O	LVDS data lane 15
DOUTP15	T9	O	LVDS data lane 15
DOUTM16	U10	O	LVDS data lane 16
DOUTP16	U9	O	LVDS data lane 16
DVDD_1P2	A7, B8, C8, D8, F7, G7, M7, N7, R8, T6, T8, U8, V7	P	1.2-V digital supply voltage
DVDD_1P8	E8, F8, G8, J10, M8, N8, P8	P	1.8-V digital supply voltage
DVSS	A8, D7, E7, H7, H8, J7, J8, K7, K8, K10, L7, L8, R6, V8	G	Digital ground
FCLKM	K9	O	LVDS frame clock output
FCLKP	J9	O	LVDS frame clock output
INM1	B3	I	Differential analog input 1 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP1	A3	I
INM2	A1	I	Differential analog input 2 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP2	A2	I
INM3	B1	I	Differential analog input 3 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP3	B2	I
INM4	D3	I	Differential analog input 4 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP4	C3	I
INM5	C1	I	Differential analog input 5 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP5	C2	I
INM6	D1	I	Differential analog input 6 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP6	D2	I
INM7	E1	I	Differential analog input 7 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP7	E2	I
INM8	E3	I	Differential analog input 8 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP8	E4	I
INM9	F1	I	Differential analog input 9 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP9	F2	I
INM10	F3	I	Differential analog input 10 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP10	F4	I
INM11	G1	I	Differential analog input 11 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP11	G2	I
INM12	G3	I	Differential analog input 12 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP12	G4	I
INM13	H1	I	Differential analog input 13 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP13	H2	I
INM14	H3	I	Differential analog input 14 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP14	H4	I
INM15	J1	I	Differential analog input 15 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP15	J2	I
INM16	J3	I	Differential analog input 16 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP16	J4	I
INM17	K1	I	Differential analog input 17 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP17	K2	I
INM18	K3	I	Differential analog input 18 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP18	K4	I
INM19	L1	I	Differential analog input 19 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP19	L2	I
INM20	L3	I	Differential analog input 20 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP20	L4	I
INM21	M1	I	Differential analog input 21 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP21	M2	I
INM22	M3	I	Differential analog input 22 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP22	M4	I
INM23	N1	I	Differential analog input 23 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP23	N2	I
INM24	N3	I	Differential analog input 24 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP24	N4	I
INM25	P1	I	Differential analog input 25 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP25	P2	I
INM26	P3	I	Differential analog input 26 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP26	P4	I
INM27	R1	I	Differential analog input 27 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP27	R2	I
INM28	R3	I	Differential analog input 28 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP28	T3	I
INM29	T1	I	Differential analog input 29 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP29	T2	I
INM30	U1	I	Differential analog input 30 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP30	U2	I
INM31	V1	I	Differential analog input 31 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP31	V2	I
INM32	U3	I	Differential analog input 32 pins; see Table 1 for mapping to external inputs in 8-, 16-, and 32-input modes
INP32	V3	I
NC	D5, E5, N5, P5	—	Do not connect; leave floating.
PDN_FAST	C6	I	Fast power-down control pin (active high) with an internal pulldown resistor of 20 kΩ. For active high, a 1.8-V logic level is recommended.
PDN_GBL	C7	I	Global power-down control input (active high) with an internal pulldown resistor of 20 kΩ. For active high, a 1.8-V logic level is recommended.
SPI_DIG_EN	B6	I	Reserved for digital functionality. This pin can be left floating or be connected to the 1.8-V supply. This pin has an internal pullup resistor of 20 kΩ.
RESET	A6	I	Hardware reset pin (active high) with an internal pulldown resistor of 20 kΩ. For active high, a 1.8-V logic level is recommended.
SCLK	B7	I	Serial interface clock input with an internal pulldown resistor of 20 kΩ. For active high, a 1.8-V logic level is recommended.
SDIN	A5	I	Serial interface data input with an internal pulldown resistor of 20 kΩ. For active high, a 1.8-V logic level is recommended.
SDOUT	C5	O	Serial interface data readout. High impedance when readout is disabled. 1.8-V logic level is recommended.
SEN	B5	I	Serial interface enable with an internal pullup resistor of 20 kΩ. 1.8-V logic level is recommended.
TX_TRIG	D6	I	1.8-V logic; a pulse on TX_TRIG must be applied after power-up to ensure that all internal clock dividers are synchronized⁽¹⁾.Has an internal pull-down resistor of 20 kΩ to ground.
SYNCM_SERDES	P7	I	Frame synchronization input as per JESD204B standard
SYNCP_SERDES	R7	I	Frame synchronization input as per JESD204B standard
SYSREFM_SERDES	T7	I	Frame clock and local multiframe clock (LMFC) synchronization input as per JESD204B, subclass 1 standard
SYSREFP_SERDES	U7	I
VCM	F5	O	Common-mode output pin for biasing analog input signals. Connect a 10-µF capacitor to ground.

(1) See the Device Synchronization Using TX_TRIG section for more details on synchronization using TX_TRIG.

(2) If the JESD interface is not used, then do not connect the CMLx, SYNCx, and SYSREFx pins. If the LVDS interface is not used, then do not connect DOUTx, DCLKx, and FCLKx.