8.4.5 Power Modes

The ADS52J90 can be configured via SPI or pin settings to a global power-down mode and via pin settings to a fast power-down (standby mode). During these two modes (global and standby power-down), different internal functions stay powered up, resulting in different power consumption and wake-up times.

In standby mode, all LVDS data lanes are powered down. The bit clock and frame clock lanes remain enabled to save time to sync again on the receiver side. However, in global power-down mode all lanes are powered down and thus this mode requires more time to wake-up because the bit clock and frame clock lanes must sync again with the receiver device.

The device consists of the following key blocks:

• Band-gap circuit,
• Serial interface,
• Reference voltage and current generator,
• ADC analog block that performs a sampling and conversion,
• ADC digital block that includes all the digital post processing blocks (such as the offset, gain, digital HPF, and so forth),
• LVDS data serializer and buffer that converts the ADC parallel data to a serial stream,
• LVDS frame and clock serializer and buffer, and
• PLL (phase-locked loop) that generates a high-frequency clock for both the ADC and serializer.

Of all these blocks, only the band-gap and serial interface block are not powered down using the power-down pins or bits. Table 32 lists which blocks in the ADC are powered down using different pins and bits.