ZHCSDS3C May 2015 – April 2018 ADS52J90
PRODUCTION DATA.
The ADC data coming out of the LVDS outputs can be replaced by different kinds of test patterns. Note that the test patterns replace the data streaming out of the ADCs (more specifically, the DIGRES1 signal). Therefore, in 16-, 8-, and 32-channel input modes, the pattern that occurs on a per-channel basis can be different for some test patterns. The different test patterns are described in Table 33.
| TEST PATTERN MODE | PROGRAMMING THE MODE | TEST PATTERNS REPLACE(1) | |
|---|---|---|---|
| THE SAME PATTERN MUST BE COMMON TO ALL DATA LINES | THE PATTERN IS SELECTIVELY REQUIRED ON ONE OR MORE DATA LINE | ||
| All 0s | Set the mode using PAT_MODES[2:0] | Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] | Zeros in all bits (00000000000000) of DIGRESx |
| All 1s | Set the mode using PAT_MODES[2:0] | Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] | Ones in all bits (11111111111111) of DIGRESx |
| Deskew | Set the mode using PAT_MODES[2:0] | Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] | DIGRESx word is replaced by alternate 0s and 1s (01010101010101) |
| Sync | Set the mode using PAT_MODES[2:0] | Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] | DIGRESx word is replaced by half 1s and half 0s (11111110000000) |
| Custom | Set the mode using PAT_MODES[2:0]. Set the desired custom pattern using the CUSTOM_PATTERN register control. | Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] | The word written in the CUSTOM_PATTERN control (taken from the MSB side) replaces DIGRESx.
(For instance, CUSTOM_PATTERN = 1100101101011100 and DIGRESx = 11001011010111 when the serialization factor is 14.) |
| Ramp | Set the mode using PAT_MODES[2:0] | Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] | The ADCOUTx word (not the DIGRESx word) is replaced by a word that increments by 1 LSB every conversion clock starting at negative full-scale, increments until positive full-scale, and wraps back to negative full-scale. |
| Toggle | Set the mode using PAT_MODES[2:0] | Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] | The DIGRESx word alternates between two words that are all 1s and all 0s. At each setting of the toggle pattern, the start word can either be all 0s or all 1s. (Alternate between 11111111111111 and 00000000000000.) |
| PRBS | Set SEL_PRBS_PAT_GBL = 1. Select either custom or ramp pattern with PAT_MODES[2:0]. Enable PRBS mode using PRBS_EN. Select the desired PRBS mode using PRBS_MODE. Reset the PRBS generator with PRBS_SYNC. | Set PAT_SELECT_IND = 1. Select either custom or ramp pattern with PAT_LVDSx[2:0]. Enable PRBS mode on DOUTx with the PAT_PRBS_LVDSx control. Select the desired PRBS mode using PRBS_MODE. Reset the PRBS generator with PRBS_SYNC. | A 16-bit pattern is generated by a 23-bit (or 9-bit) PRBS pattern generator (taken from the MSB side) and replaces the DIGRESx word. |
All patterns listed in Table 33 (except the PRBS pattern) can also be forced on the frame clock output line by using PAT_MODES_FCLK[2:0]. To force a PRBS pattern on the frame clock, use the SEL_PRBS_PAT_FCLK, PRBS_EN, and PAT_MODES_FCLK register controls.
The ramp, toggle, and pseudo-random sequence (PRBS) test patterns can be reset or synchronized by providing a synchronization pulse on the TX_TRIG pin or by setting and resetting a specific register bit.
These test patterns also function as transport layer test patterns for the JESD204B interface.