8.5.1.2 Register Readout

The device includes an option where the contents of the internal registers can be read back. This readback can be useful as a diagnostic test to verify the serial interface communication between the external controller and AFE. First, the REG_READ_EN bit must be set to 1. Then, initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read. The data bits are don’t care. The device outputs the contents (D[15:0]) of the selected register on the SDOUT pin. For lower-speed SCLKs, SDOUT can be latched on the SCLK rising edge. For higher-speed SCLKs, latching SDOUT at the next SCLK falling edge is preferable. The read operation timing diagram is shown in Figure 93. In readout mode, the REG_READ_EN bit can be accessed with SDIN, SCLK, and SEN. To enable serial register writes, set the REG_READ_EN bit back to 0.

Figure 93. Serial Interface Register, Read Operation

The device SDOUT buffer is 3-stated and is only enabled when the REG_READ_EN bit is enabled. SDOUT pins from multiple devices can therefore be tied together without any pullup resistors. The SN74AUP1T04 level shifter can be used to convert 1.8-V logic to 2.5-V or 3.3-V logic, if necessary.