米6体育平台手机版

SLAS669E September 2010 – may 2020 ADS5400-SP

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

HFS|100
- MCQF018C

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.8 Interleaving Adjustments

Typical values at T_A = 25°C, Min and Max values over full temperature range T_MIN = –55°C to T_MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 V_PP differential clock (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Offset Adjustments
	Resolution		9			Bits
	LSB magnitude	at full scale range of 2V_PP		120		µV
DNL	Differential linearity error		-2.5		2.5	LSB
INL	Integral Non-Linearity error		-3		3	LSB
	Recommended Min Offset Setting	from default offset value, to maintain AC performance		-8		mV
	Recommended Max Offset Setting	from default offset value, to maintain AC performance		8		mV
Gain Adjustments
	Resolution		12			Bits
	LSB magnitude			120		µV
DNL	Differential linearity error		-4	-1.2, +0.5	4	LSB
INL	Integral Non-Linearity error		-8	-2, +1	8	LSB
	Min Gain Setting			1.52		V_PP
	Max Gain Setting			2		V_PP
Input Clock Fine Phase Adjustment
	Resolution		6			Bits
	LSB magnitude			116		fs
DNL	Differential linearity error		-2		2.5	LSB
INL	Integral Non-Linearity error		-2.5		4	LSB
	Max Fine Clock Skew setting			7.4		ps
Input Clock Coarse Phase Adjustment
	Resolution		5			Bits
	LSB magnitude			2.4		ps
DNL	Differential linearity error		-1		1	LSB
INL	Integral Non-Linearity error		-1		5	LSB
	Max Coarse Clock Skew setting			73		ps

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTA transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit. Bus B is not active in single bus mode.

Figure 1. Single Bus Mode

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.

Figure 2. Dual Bus Mode - Aligned, CLKOUT Divide By 2

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.

Figure 3. Dual Bus Mode - Staggered, CLKOUT Divide By 2

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.

Figure 4. Dual Bus Mode - Aligned, CLKOUT Divide By 4

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.

Figure 5. Dual Bus Mode - Staggered, CLKOUT Divide By 4