10.1 Layout Guidelines

The evaluation board provides a guideline of how to lay out the board to obtain the maximum performance from the ADS5400-SP. General design rules, such as the use of multilayer boards, single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors, should be applied. The input traces should be isolated from any external source of interference or noise, including the digital outputs as well as the clock traces. The clock signal traces should also be isolated from other signals, especially in applications where low jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when considering the heat dissipation of the device. The thermal heat sink should be soldered to the board as described in the section.

Figure 42 is a section of the layout of the ADS5400-SP that illustrates good layout practices for the clocking, analog input, and digital outputs. In this example, the analog input enters from the top left while the clocking enters from the left center, keeping the clock signal away from the analog signals so as to not allow coupling between the analog signal and the clock signal. One thing to notice on the layout of the differential traces is the symmetry of the trace routing between the two sides of the differential signals.

The digital outputs are routed off to the right, so as to keep the digital signals away from the analog inputs and away from the clock. Notice the circuitous routing added to some of the LVDS differential traces but not to others; this is the equalize the lengths of the routing across all of the LVDS traces so as to preserve the setup/hold timing at the end of the digital signal routings. If the timing closure in the receiving device (such as an FPGA or ASIC) has enough timing margin, then the circuitous routing to equalize trace lengths may not be necessary.