7.4.1 Output Bus and Clock Options

The ADS5400-SP has two buses, A and B. Using register 0x02, a single or dual bus output can be selected. In single-bus mode, bus A is used at the full clock rate, while in two-bus mode, data is multiplexed at half the clock rate on A and B. While in single bus mode, CLKOUTA is at frequency CLKIN/2 and a DDR interface is achieved. In two-bus mode, CLKOUTA/CLKOUTB can be either at frequency CLKIN/2 or CLKIN/4, providing options for an SDR or DDR interface. The ADC provides 12 LVDS-compatible data outputs (D11 to D0; D11 is the MSB and D0 is the LSB), a data-ready signal (CLKOUT), and an over-range indicator (OVR) on each bus. It is recommended to use the CLKOUT signal to capture the output data of the ADS5400. Both two's complement and offset binary are available output formats, in register 0x05.

The capacitive loading on the digital outputs should be minimized. Higher capacitance shortens the data-valid timing window. The values given for timing were obtained with an estimated 3.5-pF of differential parasitic board capacitance on each LVDS pair.