7.1 Overview

The ADS5400-SP is a 12-bit, 1-GSPS, monolithic pipeline ADC. Its bipolar transistor analog core operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible digital outputs. The conversion process is initiated by the falling edge of the external input clock. At the sampling instant, the differential input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of 7 - 8.5 clock cycles (output mode dependent), after which the output data is available as a 12-bit parallel word, coded in offset binary or two's complement format.

The user can select to accept the data at the full sample rate using one bus (bus A, latency 7 cycles), or demultiplex the data into two buses (bus A and B, latency 7.5 or 8.5 cycles) at half rate. A serial peripheral interface (SPI) is provided for adjusting operational modes, as well as for calibrations of analog gain, analog offset and clock phase for inter-leaving multiple ADS5400-SP. Die temperature readout using the SPI is provided. SYNC and RESET modes exist for synchronizing output data across multiple ADS5400-SP.