SLAS669E September   2010  – may 2020 ADS5400-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Interleaving Adjustments
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Configuration
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Analog Input Over-Range Recovery Error
      4. 7.3.4  Clock Inputs
      5. 7.3.5  Over Range
      6. 7.3.6  Data Scramble
      7. 7.3.7  Test Patterns
      8. 7.3.8  Die Identification and Revision
      9. 7.3.9  Die Temperature Sensor
      10. 7.3.10 Interleaving
        1. 7.3.10.1 Gain Adjustment
        2. 7.3.10.2 Offset Adjustment
        3. 7.3.10.3 Input Clock Coarse Phase Adjustment
        4. 7.3.10.4 Input Clock Fine Phase Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Bus and Clock Options
      2. 7.4.2 Reset and Synchronization
      3. 7.4.3 LVDS
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. Table 2. Instruction Byte of the Serial Interface
    6. 7.6 Serial Register Map
      1. 7.6.1 Description of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADS5400-SP
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Specifications
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

HSF package(100)
CFP (TBAR) 100-pins
Top View
ADS5400-SP po_las611.gif

Pin Functions

PIN DESCRIPTION
NAME NO.
AINP, AINN 94, 95 Analog differential input signal (positive, negative). Includes 100-Ω differential load on-chip.
AVDD5 1, 76, 86, 90, 92, 97, 99 Analog power supply (5 V)
AVDD3 2, 7, 9, 85 Analog power supply (3.3 V)
DVDD3 24, 38, 50, 64 Output driver power supply (3.3 V)
AGND 3, 6, 8, 84, 88, 91, 93, 96, 98, 100 Analog Ground
DGND 25, 39, 51, 65 Digital Ground
CLKINP, CLKINN 4, 5 Differential input clock (positive, negative). Includes 160-Ω differential load on-chip.
DA0N, DA0P 46, 47 Bus A, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
DA1N–DA10N, DA1P-DA10P 48-49, 52-59, 62-63, 66-73 Bus A, LVDS digital output pairs (bits 1- 10)
DA11N, DA11P 74, 75 Bus A, LVDS digital output pair, most-significant bit (MSB)
CLKOUTAN, CLKOUTAP 60, 61 Bus A, Clock Output (Data ready), LVDS output pair
DB0N, DB0P 40, 41 Bus B, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
DB1N–DB10N, DB1P-DB10P 14-23, 28-37 Bus B, LVDS digital output pairs (bits 1- 10)
DB11N, DB11P 12, 13 Bus B, LVDS digital output pair, most-significant bit (MSB)
CLKOUTBN, CLKOUTBP 26, 27 Bus B, Clock Output (Data ready), LVDS output pair
OVRAN, OVRAP 44, 45 Bus A, Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range. Becomes SYNCOUTA when SYNC mode is enabled in register 0x05.
OVRBN, OVRBP 42, 43 Bus B, Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range. Becomes SYNCOUTB when SYNC mode is enabled in register 0x05.
RESETN, RESETP 10, 11 Digital Reset Input, LVDS input pair. Inactive if logic low. When clocked in a high state, this is used for resetting the polarity of CLKOUT signal pair(s). If SYNC mode is enabled in register 0x05, this input also provides a SYNC time-stamp with the data sample present when RESET is clocked by the ADC, as well as CLKOUT polarity reset. Includes 100-Ω differential load on-chip.
SCLK 78 Serial interface clock.
SDIO 79 Bi-directional serial interface data in 3-pin mode (default) for programming/reading internal registers. In 4-pin interface mode (reg 0x01), the SDIO pin is an input only.
SDO 80 Uni-directional serial interface data in 4-pin mode (reg 0x01) provides internal register settings. The SDO pin is in high-impedance state in 3-pin interface mode (default).
SDENB 77 Active low serial data enable, always an input. Use to enable the serial interface. Internal 100kΩ pull-up resistor.
VREF 87 Reference voltage input (2V nominal). A 0.1μF capacitor to AGND is recommended, but not required.
ENA1BUS 81(1) Enable single output bus mode (2-bus mode is default), active high. This pin is logic OR'd with addr 0x02h bit<0>.
ENPWD 82(1) Enable Powerdown, active high. Places the converter into power-saving sleep mode when high. This pin is logic OR'd with addr 0x05h bit<6>.
ENEXTREF 83(1) Enable External Reference Mode, active high. Device uses an external voltage reference when high. This pin is logic OR'd with addr 0x05h bit<2>.
VCM 89 Analog input common mode voltage, Output (for DC-coupled applications, nominally 2.5V). A 0.1μF capacitor to AGND is recommended, but not required.
(1) This pin contains an internal ~40kΩ pull-down resistor, to ground.
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