7.4.2 Reset and Synchronization

Referencing the timing diagrams starting in Figure 1, the polarity of CLKOUT with respect to the sample N data output transition is undetermined because of the unknown startup logic level of the clock divider that generates the CLKOUT signal, whether in frequency CLKIN/2 or CLKIN/4 mode. The polarity of CLKOUT could invert when power is cycled off/on. If a defined CLKOUT polarity is required, the RESET input pins are used to reset the clock divider to a known state after power on with a reset pulse. A RESET is not commonly required when using only one ADS5400 because a one sample uncertainty at startup is not usually a problem.

NOTE: initial samples capture RESET = HIGH on the rising edge of CLKINP. This is being corrected for final samples and will reflect the diagram as drawn, with RESET = HIGH captured on falling edge of CLKINP.

In addition to CLKOUT alignment using RESET, a synchronization mode is provided in register 0x05. In this mode, the OVR output becomes the SYNCOUT. The SYNCOUT will indicate which sample was present when the RESET input pulse was captured in a HIGH state. The OVR indicator is not available when sync mode is enabled. In single bus mode, only SYNCOUTA is used. In dual bus mode, only SYNCOUTB is used.