SLAS611C October   2009  – January 2016 ADS5400

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Interleaving Adjustments
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Configuration
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Analog Input Over-Range Recovery Error
      4. 7.3.4  Clock Inputs
      5. 7.3.5  Over Range
      6. 7.3.6  Data Scramble
      7. 7.3.7  Test Patterns
      8. 7.3.8  Die Identification and Revision
      9. 7.3.9  Die Temperature Sensor
      10. 7.3.10 Interleaving
        1. 7.3.10.1 Gain Adjustment
        2. 7.3.10.2 Offset Adjustment
        3. 7.3.10.3 Input Clock Coarse Phase Adjustment
        4. 7.3.10.4 Input Clock Fine Phase Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Bus and Clock Options
      2. 7.4.2 Reset and Synchronization
      3. 7.4.3 LVDS
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1 Serial Register Map
      2. 7.6.2 Description of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADS5400
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PowerPAD™ Package
      1. 10.3.1 Assembly Process
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

PZP Package
100-Pin HTQFP With Exposed Thermal Pad
Top View
ADS5400 po_las611.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
3, 6, 8, 84, 88, 91, 93, 96, 98, 100 AGND Ground Analog ground
94, 95 AINP, AINN Input Analog differential input signal (positive, negative). Includes 100-Ω differential load on-chip.
2, 7, 9, 85 AVDD3 Supply Analog power supply (3.3 V)
1, 76, 86, 90, 92, 97, 99 AVDD5 Supply Analog power supply (5 V)
4, 5 CLKINP, CLKINN Input Differential input clock (positive, negative). Includes 160-Ω differential load on-chip.
60, 61 CLKOUTAN, CLKOUTAP Output Bus A, Clock output (Data ready), LVDS output pair
26, 27 CLKOUTBN, CLKOUTBP Output Bus B, Clock output (Data ready), LVDS output pair
46, 47 DA0N, DA0P Output Bus A, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
48-49, 52-59, 62-63, 66-73 DA1N–DA10N, DA1P-DA10P Output Bus A, LVDS digital output pairs (bits 1- 10)
74, 75 DA11N, DA11P Output Bus A, LVDS digital output pair, most-significant bit (MSB)
40, 41 DB0N, DB0P Output Bus B, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
14-23, 28-37 DB1N–DB10N, DB1P-DB10P Output Bus B, LVDS digital output pairs (bits 1- 10)
12, 13 DB11N, DB11P Output Bus B, LVDS digital output pair, most-significant bit (MSB)
25, 39, 51, 65 DGND Ground Digital ground
24, 38, 50, 64 DVDD3 Supply Output driver power supply (3.3 V)
81(1) ENA1BUS Input Enable single output bus mode (2-bus mode is default), active high. This pin is logic OR'd with addr 0x02h bit<0>.
83(1) ENEXTREF Input Enable External Reference Mode, active high. Device uses an external voltage reference when high. This pin is logic OR'd with addr 0x05h bit<2>.
82(1) ENPWD Input Enable Powerdown, active high. Places the converter into power-saving sleep mode when high. This pin is logic OR'd with addr 0x05h bit<6>.
44, 45 OVRAN, OVRAP Output Bus A, Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range. Becomes SYNCOUTA when SYNC mode is enabled in register 0x05.
42, 43 OVRBN, OVRBP Output Bus B, Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range. Becomes SYNCOUTB when SYNC mode is enabled in register 0x05.
10, 11 RESETN, RESETP Input Digital Reset Input, LVDS input pair. Inactive if logic low. When clocked in a high state, this is used for resetting the polarity of CLKOUT signal pair(s). If SYNC mode is enabled in register 0x05, this input also provides a SYNC time-stamp with the data sample present when RESET is clocked by the ADC, as well as CLKOUT polarity reset. Includes 100-Ω differential load on-chip.
78 SCLK Input Serial interface clock.
77 SDENB Input Active low serial data enable, always an input. Use to enable the serial interface. Internal 100kΩ pull-up resistor.
79 SDIO Input/Output Bidirectional serial interface data in 3-pin mode (default) for programming/reading internal registers. In 4-pin interface mode (reg 0x01), the SDIO pin is an input only.
80 SDO Output Unidirectional serial interface data in 4-pin mode (reg 0x01) provides internal register settings. The SDO pin is in high-impedance state in 3-pin interface mode (default).
89 VCM Input/Output Analog input common mode voltage, Output (for DC-coupled applications, nominally 2.5 V). A 0.1-μF capacitor to AGND is recommended, but not required.
87 VREF Input Reference voltage input (2 V nominal). A 0.1-μF capacitor to AGND is recommended, but not required.
(1) This pin contains an internal ~40kΩ pull-down resistor, to ground.
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