米6体育平台手机版

SLAS611C October 2009 – January 2016 ADS5400

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PZP|100
- MPQF053D

散热焊盘机械数据 (封装 | 引脚)

PZP|100
- PPTD102E

订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

				MIN	MAX	UNIT
Supply voltage	AVDD5 to GND				6	V
	AVDD3 to GND				5	V
	DVDD3 to GND				5	V
	AINP, AINN to GND⁽²⁾	Voltage difference between pin and ground		0.5	4.5	V
	AINP to AINN⁽²⁾	Voltage difference between pins, common mode at AVDD5/2	Short duration	–0.3	(AVDD5 + 0.3)	V
			Continuous AC signal	1.25	3.75	V
			Continuous DC signal	1.75	3.25	V
Pin voltage	CLKINP, CLKINN to GND⁽²⁾	Voltage difference between pin and ground		0.5	4.5	V
	CLKINP to CLKINN⁽²⁾	Voltage difference between pins, common mode at AVDD5/2	Continuous AC signal	1.1	3.9	V
	CLKINP to CLKINN⁽²⁾	Voltage difference between pins, common mode at AVDD5/2	Continuous DC signal	2	3	V
	RESETP, RESETN to GND⁽²⁾	Voltage difference between pin and ground		–0.3	(AVDD5 + 0.3)	V
	RESETP to RESETN⁽²⁾	Voltage difference between pins	Continuous AC signal	1.1	3.9	V
	RESETP to RESETN⁽²⁾	Voltage difference between pins	Continuous DC signal	2	3	V
	Data/OVR Outputs to GND⁽²⁾	Voltage difference between pin and ground		–0.3	(DVDD3 + 0.3)	V
	SDENB, SDIO, SCLK to GND⁽²⁾			–0.3	(AVDD3 + 0.3)
	ENA1BUS, ENPWD, ENEXTREF to GND⁽²⁾			–0.3	(AVDD5 + 0.3)
Temperature	Operating			–40	85	°C
	Maximum junction , T_J				150	°C
	Storage, T_stg			–65	150	°C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime is available upon request.

(2) Valid when supplies are within recommended operating range.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
SUPPLIES
	Analog supply voltage, AVDD5	4.75	5	5.25	V
	Analog supply voltage, AVDD3	3.135	3.3	3.465	V
	Digital supply voltage, DVDD3	3.135	3.3	3.465	V
ANALOG INPUT
	Full-scale differential input range	1.52		2	V_PP
V_CM	Input common mode		AVDD5/2		V
DIGITAL OUTPUT
	Differential output load			5	pF
CLOCK INPUT
	CLK input sample rate (sine wave)	100		1000	MSPS
	Clock amplitude, differential	0.6		1.5	V_PP
	Clock duty cycle	45%	50%	55%
T_A	Open free-air temperature	–40		85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS5400	UNIT
		PZP (HTQFP)
		100 PINS
R_θJA	Junction-to-ambient thermal resistance	34.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	7.4	°C/W
R_θJB	Junction-to-board thermal resistance	9.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Typical values at T_A = 25°C, minimum and maximum values over full temperature range T_MIN = –40°C to T_MAX = 85°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input, and 1.5 V_PP differential clock (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
	Full-scale differential input range	Programmable	1.52		2	V_PP
V_CM	Common-mode input	Self-biased to AVDD5 / 2		AVDD5/2		V
R_IN	Input resistance, differential (DC)		85	100	115	Ω
C_IN	Input capacitance	Estimated to ground from each AIN pin, excluding soldered package		0.8		pF
CMRR	Common-mode rejection ratio	Common mode signal = 125 MHz		40		dB
INTERNAL REFERENCE VOLTAGE
V_REF	Reference voltage			2		V
DYNAMIC ACCURACY
	Resolution	No missing codes	12			Bits
DNL	Differential linearity error	f_IN = 125 MHz	–1	±0.7	2	LSB
INL	Integral non- linearity error	f_IN = 125 MHz	–4	±2	4.5	LSB
	Offset error	default is trimmed near 0 mV	–2.5	0	2.5	mV
	Offset temperature coefficient			0.02		mV /°C
	Gain error		–5		5	% full scale
	Gain temperature coefficient			0.03		% full scale /°C
POWER SUPPLY⁽¹⁾
I_(AVDD5)	5-V analog supply current (Bus A and B active)	f_IN = 125 MHz, f_S = 1 GSPS		220	234	mA
I_(AVDD5)	5-V analog supply current (Bus A active)	f_IN = 125 MHz, f_S = 1 GSPS		225	241	mA
I_(AVDD3)	3.3-V analog supply current (Bus A and B active)	f_IN = 125 MHz, f_S = 1 GSPS		219	234	mA
I_(AVDD3)	3.3-V analog supply current (Bus A active)	f_IN = 125 MHz, f_S = 1 GSPS		226	242	mA
I_(DVDD3)	3.3-V digital supply current (Bus A and B active)	f_IN = 125 MHz, f_S = 1 GSPS		136	154	mA
I_(DVDD3)	3.3-V digital supply current (Bus A active)	f_IN = 125 MHz, f_S = 1 GSPS		71	81	mA
	Total power dissipation (BUS A and B active)	f_IN = 125 MHz, f_S = 1 GSPS		2.28	2.45	W
	Total power dissipation (Bus A active)	f_IN = 125 MHz, f_S = 1 GSPS		2.15	2.25	W
	Total power dissipation	ENPWD = logic High (sleep enabled)		13	50	mW
	Wake-up time from sleep			1.8		ms
PSRR	Power-supply rejection ratio	1MHz injected to each supply, measured without external decoupling		50		dB
DYNAMIC AC CHARACTERISTICS
SNR	Signal-to-noise ratio	f_IN = 125 MHz	57	58.5		dBFS
		f_IN = 600 MHz	56.5	58.2
		f_IN = 850 MHz	56	57.8
		f_IN = 1200 MHz		57.6
		f_IN = 1700 MHz		55.7
SFDR	Spurious-free dynamic range	f_IN = 125 MHz	65	75		dBc
		f_IN = 600 MHz	63	72
		f_IN = 850 MHz	60	71
		f_IN = 1200 MHz		66
		f_IN = 1700 MHz		56
HD2	Second harmonic	f_IN = 125 MHz	65	78		dBc
		f_IN = 600 MHz	63	78
		f_IN = 850 MHz	60	71
		f_IN = 1200 MHz		66
		f_IN = 1700 MHz		56
HD3	Third harmonic	f_IN = 125 MHz	65	80		dBc
		f_IN = 600 MHz	63	72
		f_IN = 850 MHz	60	72
		f_IN = 1200 MHz		70
		f_IN = 1700 MHz		65
	Worst harmonic/spur (other than HD2 and HD3)	f_IN = 125 MHz	65	80		dBc
		f_IN = 600 MHz	63	72
		f_IN = 850 MHz	60	72
		f_IN = 1200 MHz		66
		f_IN = 1700 MHz		64
THD	Total Harmonic Distortion	f_IN = 125 MHz	63	71.7		dBc
		f_IN = 600 MHz	62	67
		f_IN = 850 MHz	59	66.5
		f_IN = 1200 MHz		65.1
		f_IN = 1700 MHz		55.7
SINAD	Signal-to-noise and distortion	f_IN = 125 MHz	56	58.5		dBFS
		f_IN = 600 MHz	55	58.2
		f_IN = 850 MHz	54	57.8
		f_IN = 1200 MHz		57.5
		f_IN = 1700 MHz		54.2
	Two-tone SFDR	f_IN1 = 247.5 MHz, f_IN2 = 252.5 MHz, each tone at –7 dBFS		74.6		dBFS
		f_IN1 = 247.5 MHz, f_IN2 = 252.5 MHz, each tone at –11 dBFS		80.4
		f_IN1 = 1197.5 MHz, f_IN2 = 1202.5 MHz, each tone at –7 dBFS		70
		f_IN1 = 1197.5 MHz, f_IN2 = 1202.5 MHz, each tone at –11 dBFS		78.3
ENOB	Effective number of bits (using SINAD in dBFS)	f_IN = 125 MHz	9	9.42		Bits
		f_IN = 600 MHz	8.84	9.37
		f_IN = 850 MHz	8.67	9.3
	RMS idle-channel noise	Inputs tied to common-mode		1.41		LSB rms
	RMS idle-channel noise	Inputs tied to common-mode		60.2		dBFS

(1) All power values assume LVDS output current is set to 3.5 mA.

6.6 Interleaving Adjustments

Typical values at T_A = 25°C, Minimum and maximum values over full temperature range T_MIN = –40°C to T_MAX = 85°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 V_PP differential clock (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OFFSET ADJUSTMENTS
	Resolution		9			Bits
	LSB magnitude	At full scale range of 2 V_PP		120		µV
DNL	Differential linearity error		-2.5		2.5	LSB
INL	Integral Non-Linearity error		-3		3	LSB
	Recommended Min Offset Setting	From default offset value, to maintain AC performance		-8		mV
	Recommended Max Offset Setting	From default offset value, to maintain AC performance		8		mV
GAIN ADJUSTMENTS
	Resolution		12			Bits
	LSB magnitude			120		µV
DNL	Differential linearity error		-4	-2, +1	4	LSB
INL	Integral Non-Linearity error		-8	-2, +4	8	LSB
	Min Gain Setting			1.52		V_PP
	Max Gain Setting			2		V_PP
INPUT CLOCK FINE PHASE ADJUSTMENT
	Resolution		6			Bits
	LSB magnitude			116		fs
DNL	Differential linearity error		-2		2.5	LSB
INL	Integral Non-Linearity error		-2.5		4	LBS
	Max Fine Clock Skew setting			7.4		ps
INPUT CLOCK COARSE PHASE ADJUSTMENT
	Resolution		5			Bits
	LSB magnitude			2.4		ps
DNL	Differential linearity error		-1		1	LSB
INL	Integral Non-Linearity error		-1		5	LSB
	Max Coarse Clock Skew setting			73		ps

6.7 Timing Requirements

			MIN	NOM	MAX	UNIT
t_a	Aperture delay			250		ps
	Aperture jitter, rms	Uncertainty of sample point due to internal jitter sources		125		fs
	Latency	Bus A, using Single Bus Mode		7		Cycles
		Bus A, using Dual Bus Mode Aligned		7.5
		Bus B, using Dual Bus Mode Aligned		8.5
		Bus A and B, using Dual Bus Mode Staggered		7.5
LVDS OUTPUT TIMING (DATA, CLKOUT, OVR/SYNCOUT)⁽²⁾
t_CLK	Clock period		1		10	ns
t_CLKH	Clock pulse duration, high	Assuming worst case 45/55 duty cycle	0.45			ns
t_CLKL	Clock pulse duration, low	Assuming worst case 55/45 duty cycle	0.45			ns
t_PD-CLKDIV2	Clock propagation delay	CLKIN rising to CLKOUT rising in divide by 2 mode	700	1200	1700	ps
t_PD-CLKDIV4	Clock propagation delay	CLKIN rising to CLKOUT rising in divide by 4 mode	700	1200	1700	ps
t_PD-ADATA	Bus A data propagation delay	CLKIN falling to Data Output transition	700	1400	2100	ps
t_PD-BDATA	Bus B data propagation delay	CLKIN falling to Data Output transition	700	1400	2100	ps
t_SU-SBM⁽³⁾	Setup time, single bus mode	Data valid to CLKOUT edge, 50% CLKIN duty cycle	290p	(t_CLK/2) - 185p		s
t_H-SBM	Hold time, single bus mode	CLKOUT edge to Data invalid, 50% CLKIN duty cycle	410p	(t_CLK/2) - 65p		s
t_SU-DBM	Setup time, dual bus mode	Data valid to CLKOUT edge, 50% CLKIN duty cycle	550p	t_CLK - 425p		s
t_H-DBM	Hold time, dual bus mode	CLKOUT edge to Data invalid, 50% CLKIN duty cycle	1150p	t_CLK + 175p		s
t_r	LVDS rise time	Measured 20% to 80%		400		ps
t_f	LVDS output fall time	Measured 20% to 80%		400		ps
LVDS INPUT TIMING (RESETIN)
t_RSU	RESET setup time	RESETP going HIGH to CLKINP going LOW	300			ps
t_RH	RESET hold time	CLKINP going LOW to RESETP going LOW	300			ps
	RESET input capacitance	Differential		1		pF
	RESET input current			±1		µA
SERIAL INTERFACE TIMING
t_S-SDENB	Setup time, serial enable	SDENB falling to SCLK rising	20			ns
t_H-SDENB	Hold time, serial enable	SCLK falling to SENDB rising	25			ns
t_S-SDIO	Setup time, SDIO	SDIO valid to SCLK rising	10			ns
t_H-SDIO	Hold time, SDIO	SCLK rising to SDIO transition	10			ns
f_SCLK	Frequency				10	MHz
t_SCLK	SCLK period		100			ns
t_SCLKH	Minimum SCLK high time		40			ns
t_SCLKL	Minimum SCLK low time		40			ns
t_r	Rise time	10 pF		10		ns
t_f	Fall time	10 pF		10		ns
t_DDATA	Data output delay	Data output (SDO/SDIO) delay after SCLK falling, 10-pF load	75			ns

(1) Timing parameters are specified by design or characterization, but not production tested.

(2) LVDS output timing measured with a differential 100-Ω load placed ~4 inches from the ADS5400. Measured differential load capacitance is 3.5 pF. Measurement probes and other parasitics add ~1 pF. Total approximate capacitive load is 4.5 pF differential. All timing parameters are relative to the device pins, with the loading as stated.

(3) In single bus mode at 1 GSPS (1-ns clock), the minimum output setup/hold times over process and temperature provide a minimum 700 ps of data valid window, with 300 ps of uncertainity.

6.8 Switching Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
LVDS DIGITAL OUTPUTS (DATA, OVR/SYNCOUT, CLKOUT)
V_OD	Differential output voltage (±)	Terminated 100 Ω differential	247	350	454	mV
V_OC	Common mode output voltage	Terminated 100 Ω differential	1.125	1.25	1.375	V
LVDS DIGITAL INPUTS (RESET)
V_ID	Differential input voltage (±)	Each input pin	175	350		mV
V_IC	Common mode input voltage	Each input pin	0.1	1.25	2.4	V
R_IN	Input resistance		85	100	115	Ω
C_IN	Input capacitance	Each pin to ground		0.6		pF
DIGITAL INPUTS (SCLK, SDIO, SDENB)
V_IH	High level input voltage		2		AVDD3 + 0.3	V
V_IL	Low level input voltage		0		0.8	V
I_IH	High level input current			±1		μA
I_IL	Low level input current			±1		μA
C_IN	Input capacitance			2		pF
DIGITAL INPUTS ( ENEXTREF, ENPWD, ENA1BUS)
V_IH	High level input voltage		2		AVDD5 + 0.3	V
V_IL	Low level input voltage		0		0.8	V
I_IH	High level input current	~40-kΩ internal pulldown		125		μA
I_IL	Low level input current	~40-kΩ internal pulldown		20		μA
C_IN	Input capacitance			2		pF
DIGITAL OUTPUTS (SDIO, SDO)
V_OH	High level output voltage	I_OH = 250 µA	2.8			V
V_OL	Low level output voltage	I_OL = 250 µA			0.4	V
CLOCK INPUTS
R_IN	Differential input resistance	CLKINP, CLKINN	130	160	190	Ω
C_IN	Input capacitance	Estimated to ground from each CLKIN pin, excluding soldered packaged		0.8		pF

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, to keep the CLKOUT phase the same with each RESET event. SYNCOUTA transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit. Bus B is not active in single bus mode.

Figure 1. Single Bus Mode

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.

Figure 2. Dual Bus Mode - Aligned, CLKOUT Divide By 2

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.

Figure 3. Dual Bus Mode - Staggered, CLKOUT Divide By 2

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.

Figure 4. Dual Bus Mode - Aligned, CLKOUT Divide By 4

Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit.

Figure 5. Dual Bus Mode - Staggered, CLKOUT Divide By 4

6.9 Typical Characteristics

Typical plots at T_A = 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5-V_PP differential clock, (unless otherwise noted)