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ZHCSAV9B April 2013 – January 2016 ADS5401

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

In the design of any application involving a high-speed data converter, particular attention should be paid to the design of the analog input, the clocking solution, and careful layout of the clock and analog signals. The ADS5401 evaluation module (EVM) is one practical example of the design of the analog input circuit and clocking solution, as well as a practical example of good circuit board layout practices around the ADC.

9.2 Typical Application

The analog inputs of the ADS5401 must be fully differential and biased to a desired common-mode voltage, VCM. Therefore, there will be a signal conditioning circuit for the analog input. If the amplitude of the input circuit is such that no gain is needed to make full use of the full-scale range of the ADC, then a transformer coupled circuit as in Figure 61 may be used with good results. The transformer coupling is inherently low-noise, and inherently AC-coupled so that the signal may be biased to VCM after the transformer coupling.

By using the simple drive circuit of Figure 61, uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

Figure 61. Input Drive Circuit

If signal gain is required, or the input bandwidth is to include the spectrum all the way down to DC such that AC coupling is not possible, then an amplifier-based signal conditioning circuit would be required. The figure below shows LMH3401 interfaced with ADS5401. LMH3401 is configured to have to Single-Ended input with a differential outputs follow by 1st Nyquist based low pass filter with 375MHz bandwidth. Power supply recommendations for the amplifier are also shown in Figure 62.

Figure 62. DC-Coupled Single-Ended to Differential Amplifier with 1st Nyquist Lowpass Filter

Figure 63. Recommended Differential Clock Driving Circuit

9.2.1 Design Requirements

The ADS5401 requires a fully differential analog input with a full-scale range not to exceed 1.0-V peak-to-peak, biased to a common-mode voltage of 1.9 V. In addition the input circuit must provide proper transmission line termination (or proper load resistors in an amplifier-based solution) so the input of the impedance of the ADC analog inputs should be considered as well.

The ADS5401 is capable of a typical SNR of 61.7 dBFS for input frequencies of about 100MHz. The amplifier and clocking solution will have a direct impact on performance in terms of SNR, so the amplifier and clocking solution should be selected such that the SNR performance of 61 dBFS is preserved.

9.2.2 Detailed Design Procedure

The ADS5401 has a max sample rate of 800 MHz and an input bandwidth of approximately 1200 MHz, but we will consider an application involving the first or second Nyquist zones, so we will limit the frequency bandwidth here to be under 375 MHz.

9.2.2.1 Clocking Source for ADC5401

The signal to noise ratio of the ADC is limited by three different factors: the quantization noise is typically not noticeable in pipeline converters and is 72 dB for a 12-bit ADC. The thermal noise limits the SNR at low input frequencies while the clock jitter sets the SNR for higher input frequencies.

Equation 1. ADS5401 equation_01_slas946.gif

The SNR limitation due to sample clock jitter can be calculated as following:

Equation 2. ADS5401 equation_02_slas946.gif

The total clock jitter (TJitter) has three components – the internal aperture jitter (100fs for ADS5401) which is set by the noise of the clock input buffer, the external clock jitter and the jitter from the analog input signal. It can be calculated as following:

Equation 3. ADS5401 equation_03_slas946.gif

External clock jitter can be minimized by using high quality clock sources and jitter cleaners as well as bandpass filters at the clock input while a faster clock slew rate improves the ADC aperture jitter.

The ADS5401 has a thermal noise of 61.7 dBFS and internal aperture jitter of 100 fs. The SNR depending on amount of external jitter for different input frequencies is shown in Figure 64.

For the clock input, Figure 64 shows the SNR of the device above 100 MHz begins to degrade with external clock jitter of greater than 100 fs rms, so TI recommends the clock source be limited to approximately 100 fS of rms jitter.

9.2.2.2 Amplifier Selection

The amplifier should be selected to preserve the systems SNR performance of (61 dBFS). The SNR of the system can be calculated from Equation 4.

Equation 4. ADS5401 equation_04_slas946.gif

The signal-to-noise ratio (SNR) of the amplifier and filter can be calculated from the amplitude of the signal and the bandwidth of the filter. The noise from the amplifier is band-limited by the filter with the equivalent brick-wall filter bandwidth. The amplifier and filter noise can be calculated using Equation 5.

Equation 5. ADS5401 equation_05_slas946.gif

where

E_FILTEROUT = E_NAMPOUT × √ENB
E_NAMPOUT = the output noise density of the LMH3401 (3.4 nV/√Hz)
ENB = the brick-wall equivalent noise bandwidth of the filter
V_O = the amplifier output signal

In this design we are using a 3rd order lowpass filter with 375MHz bandwidth, which gives brick-wall equivalent noise bandwidth of 431.25 MHz. Using the output noise density of LMH3401 and brick-wall equivalent bandwidth of the filter, EFILTEROUT can be calculated, equal to be 70.6 μVRMS. Substituting the values of EFILTEROUT and VO in Equation 4, SNRAMP+Filter equals 73.45 dBFS which is within our design requirements

9.2.3 Application Curve

Figure 64 shows the SNR vs input frequency and external clock signal; it can be used to estimate how much jitter on the clock signal is acceptable at a given input frequency to obtained specific SNR performance from the ADC.

Table 5. System SNR Based on ADC and Amplifier's SNR Calculations

SNR_SYSTEM	SNR_ADC	SNR_{AMP + FILTER}
57.7 dBFS	61.7 dBFS	60 dBFS
60.0 dBFS	61.7 dBFS	65 dBFS
61.1 dBFS	61.7 dBFS	70 dBFS
61.5 dBFS	61.7 dBFS	75 dBFS
61.6 dBFS	61.7 dBFS	80 dBFS

As seen in Table 5, to meet the design requirements and to have system SNR of 61 dBFS, the SNRAmp + Filter should be greater than 70 dB. Table 5 can be used to design the amplifier and filter stage of the ADC. The SNR of amplifier and filter should be greater than 70 dB to get the 61dBFS SNR for the system.

Figure 64. SNR vs Input Frequency and External Clock Jitter