SGLS378G March   2008  – October 2017 ADS5463-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADS5463-RHA
    6. 6.6  Electrical Characteristics: ADS5463-RHA
    7. 6.7  Electrical Characteristics: ADS5463-RHA
    8. 6.8  Electrical Characteristics: ADS5463-SP
    9. 6.9  Electrical Characteristics: ADS5463-SP
    10. 6.10 Electrical Characteristics: ADS5463-SP
    11. 6.11 Timing Requirements
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Configuration
      2. 8.1.2 Clock Inputs
      3. 8.1.3 Digital Outputs
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Definition of Specifications
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

HFG Package
84-Pin CFP
Top View
ADS5463-SP cqfpb_gls378.gif

Pin Functions

PIN DESCRIPTION
NAME NO.
AIN 17 Differential input signal (positive).
AIN 18 Differential input signal (negative).
AVDD5 4, 9, 14, 15, 20, 23, 25, 27, 29, 33 Analog power supply (5 V).
AVDD3 37, 39, 41 Analog power supply (3.3 V) (Suggestion for 250 MSPS: leave option to connect to 5 V for ADS5440/4 compatibility).
DVDD3 2, 54, 70 Output driver power supply (3.3 V).
GND 1, 3, 8, 10, 13, 16, 19, 21, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 43, 55, 64, 69 Ground.
CLK 11 Differential input clock (positive). Conversion initiated on rising edge.
CLK 12 Differential input clock (negative).
D0, D0 56, 57 LVDS digital output pair, least-significant bit (LSB).
D1-D3,
D1-D3 		58–63 LVDS digital output pair.
D4–D5,
D4–D5 		65–68 LVDS digital output pairs.
D6–D10,
D6–D10 		71–80 LVDS digital output pairs.
D11, D11 81, 82 LVDS digital output pair, most-significant bit (MSB).
DRY, DRY 83, 84 Data ready LVDS output pair.
NC 5–6, 46–53 No connect (5 and 6 should be left floating, 46–53 are possible future bit additions for this pinout and therefore can be connected to a digital bus or left floating).
OVR, OVR 44, 45 Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range.
RESERVED 31, 35 Reserved for possible future control features.
VREF 7 Reference voltage.
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