9.1.1 Start-Up Sequence

The steps described in Table 65 are recommended as the power-up sequence with the ADS54J20 in 20X mode (LMFS = 8224).

9.1.2 Hardware Reset

Figure 130 and Table 66 show the timing for a hardware reset.

Figure 130. Hardware Reset Timing Diagram

9.1.3 SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise, and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is 74 dBFS for a 12-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for higher input frequencies.

Equation 4.

The SNR limitation resulting from sample clock jitter can be calculated by Equation 5:

Equation 5.

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (130 f_S) is set by the noise of the clock input buffer and the external clock jitter. T_Jitter can be calculated by Equation 6:

Equation 6.

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.

The ADS54J20 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 f_S. SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 131.

Figure 131. SNR versus Input Frequency and External Clock Jitter

9.2.1 Design Requirements

9.2.1.1 Transformer-Coupled Circuits

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as ADT1-1WT or WBC1-1) can be used up to 300 MHz to achieve good phase and amplitude balances at the ADC inputs. When designing dc-driving circuits, the ADC input impedance must be considered. Figure 133 and Figure 134 show the impedance (Z_IN = R_IN || C_IN) across the ADC input pins.

Figure 133. R_IN vs Input Frequency

Figure 134. C_IN vs Input Frequency

By using the simple drive circuit of Figure 135, uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

Figure 135. Input Drive Circuit

9.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 135.

9.2.3 Application Curves

Figure 136 and Figure 137 show the typical performance at 170 MHz and 230 MHz, respectively.

SNR = 67.8 dBFS, SINAD = 67.7 dBFS, SFDR = 86 dBc, THD = 81 dBc, IL spur = 88 dBc, non HD2, HD3 spur = 89 dBc

Figure 136. FFT for 170-MHz Input Signal

SNR = 67.4 dBFS, SINAD = 67.2 dBFS, IL spur = 87 dBc, SFDR = 84 dBc, THD = 82 dBc, non HD2, HD3 spur = 90 dBc

Figure 137. FFT for 230-MHz Input Signal