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ZHCSEA4C May 2015 – December 2020 ADS54J40

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8.4.2.1 Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins, as shown in Figure 8-12. Legends used in Figure 8-12 are explained in Table 8-8. Serially shifting bits into the device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can function with SCLK frequencies from 2 MHz down to very low speeds (of a few Hertz) and also with a non-50% SCLK duty cycle.

Figure 8-12 SPI Timing Diagram

Table 8-8 SPI Timing Diagram Legend

SPI BITS	DESCRIPTION	BIT SETTINGS
R/W	Read/write bit	0 = SPI write 1 = SPI read back
M	SPI bank access	0 = Analog SPI bank (master and ADC pages) 1 = JESD SPI bank (main digital, JESD analog, and JESD digital pages)
P	JESD page selection bit	0 = Page access 1 = Register access
CH	SPI access for a specific channel of the JESD SPI bank	0 = Channel A 1 = Channel B By default, both channels are being addressed.
A[11:0]	SPI address bits	—
D[7:0]	SPI data bits	—

Table 8-9 shows the timing requirements for the serial interface signals in Figure 8-12.

Table 8-9 SPI Timing Requirements

		MIN	MAX	UNIT
f_SCLK	SCLK frequency (equal to 1 / t_SCLK)	> dc	2	MHz
t_SLOADS	SEN to SCLK setup time	100		ns
t_SLOADH	SCLK to SEN hold time	100		ns
t_DSU	SDIN setup time	100		ns
t_DH	SDIN hold time	100		ns