The ADS54J40 employs eight dc offset correction blocks (four per channel, one per interleaving core). Figure 9-3 shows a dc correction block diagram.

Figure 9-3 DC Offset Correction Block Diagram

The purpose of the dc offset correction block is to correct the dc offset of interleaving cores that mainly arise the from amplifier in the first pipeline stage. Any mismatch in dc offset among interleaving cores results in spurs at f_S / 4 and f_S / 2. The dc offset correction blocks estimate and correct the dc offset of the individual core, to an ideal mid-code value, and thereby remove the effect of offset mismatch.

The dc offset correction block can correct the dc offset of individual core up to ±1024 codes.

In applications involving dc-coupling between the ADC and the driver, the dc offset correction block can either be bypassed or frozen because the block cannot distinguish the external dc signal from the internal dc offset. Figure 9-4 shows that when bypassed, the internal dc mismatch appears at dc, and the f_S / 4 and f_S / 2 frequency points and can be as big as –40 dBFS.

Figure 9-4 FFT After Bypassing the DC Offset Correction Block