ZHCSEP7A February   2016  – March 2016 ADS54J42

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  AC Characteristics
    7. 7.7  Digital Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Typical Characteristics
    10. 7.10 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
        2. 8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3 Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3 SYSREF Signal
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
      5. 8.3.5 Power-Down Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
        1. 8.4.1.1 Serial Interface
        2. 8.4.1.2 Serial Register Write: Analog Bank
        3. 8.4.1.3 Serial Register Readout: Analog Bank
        4. 8.4.1.4 JESD Bank SPI Page Selection
        5. 8.4.1.5 Serial Register Write: JESD Bank
          1. 8.4.1.5.1 Individual Channel Programming
        6. 8.4.1.6 Serial Register Readout: JESD Bank
      2. 8.4.2 JESD204B Interface
        1. 8.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2 JESD204B Test Patterns
        3. 8.4.2.3 JESD204B Frame
        4. 8.4.2.4 JESD204B Frame
        5. 8.4.2.5 JESD204B Frame Assembly with Decimation
          1. 8.4.2.5.1 JESD Transmitter Interface
          2. 8.4.2.5.2 Eye Diagrams
    5. 8.5 Register Maps
      1. 8.5.1 Detailed Register Info
      2. 8.5.2 Example Register Writes
      3. 8.5.3 Register Descriptions
        1. 8.5.3.1 General Registers
          1. 8.5.3.1.1 Register 0h (address = 0h)
          2. 8.5.3.1.2 Register 3h (address = 3h)
          3. 8.5.3.1.3 Register 4h (address = 4h)
          4. 8.5.3.1.4 Register 5h (address = 5h)
          5. 8.5.3.1.5 Register 11h (address = 11h)
        2. 8.5.3.2 Master Page (080h) Registers
          1. 8.5.3.2.1  Register 20h (address = 20h), Master Page (080h)
          2. 8.5.3.2.2  Register 21h (address = 21h), Master Page (080h)
          3. 8.5.3.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 8.5.3.2.4  Register 24h (address = 24h), Master Page (080h)
          5. 8.5.3.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 8.5.3.2.6  Register 39h (address = 39h), Master Page (080h)
          7. 8.5.3.2.7  Register 3Ah (address = 3Ah), Master Page (080h)
          8. 8.5.3.2.8  Register 4Fh (address = 4Fh), Master Page (080h)
          9. 8.5.3.2.9  Register 53h (address = 53h), Master Page (080h)
          10. 8.5.3.2.10 Register 55h (address = 55h), Master Page (080h)
          11. 8.5.3.2.11 Register 56h (address = 56h), Master Page (080h)
          12. 8.5.3.2.12 Register 59h (address = 59h), Master Page (080h)
        3. 8.5.3.3 ADC Page (0Fh) Register
          1. 8.5.3.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)
        4. 8.5.3.4 Main Digital Page (6800h) Registers
          1. 8.5.3.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.3.4.2  Register 41h (address = 41h), Main Digital Page (6800h)
          3. 8.5.3.4.3  Register 42h (address = 42h), Main Digital Page (6800h)
          4. 8.5.3.4.4  Register 43h (address = 43h), Main Digital Page (6800h)
          5. 8.5.3.4.5  Register 44h (address = 44h), Main Digital Page (6800h)
          6. 8.5.3.4.6  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          7. 8.5.3.4.7  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          8. 8.5.3.4.8  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          9. 8.5.3.4.9  Register 52h (address = 52h), Main Digital Page (6800h)
          10. 8.5.3.4.10 Register 72h (address = 72h), Main Digital Page (6800h)
          11. 8.5.3.4.11 Register ABh (address = ABh), Main Digital Page (6800h)
          12. 8.5.3.4.12 Register ADh (address = ADh), Main Digital Page (6800h)
          13. 8.5.3.4.13 Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.3.5 JESD Digital Page (6900h) Registers
          1. 8.5.3.5.1  Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.3.5.2  Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.3.5.3  Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.3.5.4  Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.3.5.5  Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.3.5.6  Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.3.5.7  Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.3.5.8  Register 16h (address = 16h), JESD Digital Page (6900h)
          9. 8.5.3.5.9  Register 31h (address = 31h), JESD Digital Page (6900h)
          10. 8.5.3.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.3.6 JESD Analog Page (6A00h) Registers
          1. 8.5.3.6.1 Registers 12h-5h (addresses = 12h-5h), JESD Analog Page (6A00h)
          2. 8.5.3.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h)
          3. 8.5.3.6.3 Register 17h (address = 17h), JESD Analog Page (6A00h)
          4. 8.5.3.6.4 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          5. 8.5.3.6.5 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

RMP Package
72-Pin VQFNP
Top View
ADS54J42 po_sbas706.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CLOCK, SYSREF
CLKINM 28 I Negative differential clock input for the ADC
CLKINP 27 I Positive differential clock input for the ADC
SYSREFM 34 I Negative external SYSREF input
SYSREFP 33 I Positive external SYSREF input
CONTROL, SERIAL
PDN 50 I/O Power-down. Can be configured via an SPI register setting.
Can be configured to fast overrange output for channel A via the SPI.
RESET 48 I Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.
SCLK 6 I Serial interface clock input
SDIN 5 I Serial interface data input
SDOUT 11 O Serial interface data output.
Can be configured to fast overrange output for channel B via the SPI.
SEN 7 I Serial interface enable
DATA INTERFACE
DA0M 62 O JESD204B serial data negative outputs for channel A
DA1M 59
DA2M 56
DA3M 54
DA0P 61 O JESD204B serial data positive outputs for channel A
DA1P 58
DA2P 55
DA3P 53
DB0M 65 O JESD204B serial data negative outputs for channel B
DB1M 68
DB2M 71
DB3M 1
DB0P 66 O JESD204B serial data positive outputs for channel B
DB1P 69
DB2P 72
DB3P 2
SYNC 63 I Synchronization input for the JESD204B port
INPUT, COMMON MODE
INAM 41 I Differential analog negative input for channel A
INAP 42 I Differential analog positive input for channel A
INBM 14 I Differential analog negative input for channel B
INBP 13 I Differential analog positive input for channel B
VCM 22 O Common-mode voltage, 2.1 V.
Note that analog inputs are internally biased to this pin through 600 Ω (effective), no external connection from the VCM pin to the INxP or INxM pin is required.
POWER SUPPLY
AGND 18, 23, 26, 29, 32, 36, 37 I Analog ground
AVDD 9, 12, 15, 17, 25, 30, 35, 38, 40, 43, 44, 46 I Analog 1.9-V power supply
AVDD3V 10, 16, 24, 31, 39, 45 I Analog 3.0-V power supply for the analog buffer
DGND 3, 52, 60, 67 I Digital ground
DVDD 8, 47 I Digital 1.9-V power supply
IOVDD 4, 51, 57, 64, 70 I Digital 1.15-V power supply for the JESD204B transmitter
NC, RES
NC 19-21 — Unused pins, do not connect
RES 49 I Reserved pin. Connect to DGND.
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