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ZHCSEP7A February 2016 – March 2016 ADS54J42

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8 Detailed Description

8.1 Overview

The ADS54J42 is a low-power, wide-bandwidth, 14-bit, 625-MSPS, dual-channel, analog-to-digital converter (ADC). The ADS54J42 employs four interleaving ADCs for each channel to achieve a noise floor of –157 dBFS/Hz. The ADS54J42 uses TI's proprietary interleaving and dither algorithms to achieve a clean spectrum with a high spurious-free dynamic range (SFDR). The device also offers various programmable decimation filtering options for systems requiring higher signal-to-noise ratio (SNR) and SFDR over a wide range of frequencies.

Analog input buffers isolate the ADC driver from glitch energy generated from sampling process, thereby simplify the driving network on-board. The JESD204B interface reduces the number of interface lines with two-lane and four-lane options, allowing a high system integration density. The JESD204B interface operates in subclass 1, enabling multi-chip synchronization with the SYSREF input.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Analog Inputs

The ADS54J42 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source that enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to VCM using 600-Ω resistors, allowing for ac-coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.475 V) and (VCM – 0.475 V), resulting in a 1.9-V_PP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 1.2 GHz. An equivalent analog input network diagram is shown in Figure 58.

Figure 58. Analog Input Network

The input bandwidth shown in Figure 59 is measured with respect to a 50-Ω differential input termination at the ADC input pins.

Figure 59. Transfer Function versus Frequency

8.3.2 DDC Block

The ADS54J42 has an optional DDC block that can be enabled via an SPI register write. Each ADC channel is followed by a DDC block consisting of three different decimate-by-2 and decimate-by-4 finite impulse response (FIR) half-band filter options. The different decimation filter options can be selected via SPI programming.

Figure 60 shows the signal processing done inside the DDC block of the ADS54J42.

1. In IQ decimate-by-4 mode, the mixer frequency is fixed at f_mix = f_S / 4. For f_S = 625 MSPS and f_mix = 156.25 MHz.

Figure 60. DDC Block

8.3.2.1 Decimate-by-2 Filter

This decimation filter has 41 taps. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.05 dB. Table 1 shows corner frequencies for the low-pass and high-pass filter options.

Table 1. Corner Frequencies for the Decimate-by-2 Filter

CORNERS (dB)	LOW PASS	HIGH PASS
–0.1	0.202 × f_S	0.298 × f_S
–0.5	0.210 × f_S	0.290 × f_S
–1	0.215 × f_S	0.285 × f_S
–3	0.227 × f_S	0.273 × f_S

Figure 61 and Figure 62 show the frequency response of the decimate-by-2 filter from dc to f_S / 2.

Figure 61. Decimate-by-2 Filter Response

Figure 62. Decimate-by-2 Filter Response (Zoomed)

8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer

This band-pass decimation filter consists of a digital mixer and three concatenated FIR filters with a combined latency of approximately 28 output clock cycles. The alias band attenuation is approximately 55 dB and the pass-band flatness is ±0.1 dB. By default after reset, the band-pass filter is centered at f_S / 16. Using the SPI, the center frequency can be programmed at N × f_S / 16 (where N = 1, 3, 5, or 7). Table 2 shows corner frequencies for two extreme options.

Table 2. Corner frequencies for the Decimate-by-4 Filter

CORNERS (dB)	CORNER FREQUENCY AT LOWER SIDE (Center Frequency f_S / 16)	CORNER FREQUENCY AT HIGHER SIDE (Center Frequency f_S / 16)
–0.1	0.011 × f_S	0.114 × f_S
–0.5	0.010 × f_S	0.116 × f_S
–1	0.008 × f_S	0.117 × f_S
–3	0.006 × f_S	0.120 × f_S

Figure 63 and Figure 64 show the frequency response of the decimate-by-4 filter for center frequencies f_S / 16 and 3 × f_S / 16 (N = 1 and N = 3, respectively).

Figure 63. Decimate-by-4 Filter Response

Figure 64. Decimate-by-4 Filter Response (Zoomed)

8.3.2.3 Decimate-by-4 Filter with IQ Outputs

In this configuration, the DDC block includes a fixed digital f_S / 4 mixer. Thus, the IQ pass band is approximately ±0.11 f_S, centered at f_S / 4. This decimation filter has 41 taps with a latency of approximately ten output clock cycles. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.05 dB. Table 3 shows the corner frequencies for a low-pass, decimate-by-4 IQ filter.

Table 3. Corner Frequencies for a Decimate-by-4 IQ Output Filter

CORNERS (dB)	LOW PASS
–0.1	0.107 × f_S
–0.5	0.112 × f_S
–1	0.115 × f_S
–3	0.120 × f_S

Figure 65 and Figure 66 show the frequency response of a decimate-by-4 IQ output filter from dc to f_S / 2.

Figure 65. Decimate-by-4 IQ Output Filter Response

Figure 66. Decimate-by-4 IQ Output Filter Response (Zoomed)

8.3.3 SYSREF Signal

The SYSREF signal is a periodic signal that is sampled by the ADS54J42 device clock and used to align the boundary of the local multi-frame clock inside the data converter. SYSREF is required to be a sub-harmonic of the local multiframe clock (LMFC) internal timing. To meet this requirement, the timing of SYSREF is dependent on the device clock frequency and the LMFC frequency, as determined by the selected DDC decimation and frames per multi-frame settings. The SYSREF signal is recommended to be a low-frequency signal in the range of 1 MHz to 5 MHz to reduce coupling to the signal path both on the printed circuit board (PCB) as well as internal to the device.

The external SYSREF signal must be a sub-harmonic of the internal LMFC clock, as shown in Equation 1 and Table 4.

Equation 1. SYSREF = LMFC / 2^N

where

N = 0, 1, 2, and so forth

Table 4. LMFSC Clock Frequency

LMFS CONFIGURATION	DECIMATION	LMFC CLOCK⁽¹⁾⁽²⁾
4211	—	f_S / K
4244	—	(f_S / 4) / K
8224	—	(f_S / 4) / K
4222	2X	(f_S / 4) / K
2242	2X	(f_S / 4) / K
2221	4X	(f_S / 4) / K
2441	4X (IQ)	(f_S / 4) / K
4421	4X (IQ)	(f_S / 4) / K
1241	4X	(f_S / 4) / K

(1) K = Number of frames per multi-frame (JESD digital page 6900h, address 06h, bits 4-0).

(2) f_S = sampling (device) clock frequency.

For example, if LMFS = 8224, the default value of K is 8 + 1 = 9 (the actual value for K = the value set in the SPI register + 1). If the device clock frequency is f_S = 625 MSPS, then the local multi-frame clock frequency becomes (625 / 4) / 9 = 17.361111 MHz. The SYSREF signal frequency can be chosen as LMFC frequency / 8 = 2.1701389 MHz.

8.3.4 Overrange Indication

The ADS54J42 provides a fast overrange indication that can be presented in the digital output data stream via SPI configuration. Alternatively, if not used, the SDOUT (pin 11) and PDN (pin 50) pins can be configured via the SPI to output the fast OVR indicator.

The JESD 8b, 10b encoder receives 16-bit data that is formed by 14-bit ADC data padded with two 0s as LSBs. When the FOVR indication is embedded in the output data stream, the LSB of the 16-bit data stream going to the 8b, 10b encoder is replaced, as shown in Figure 67.

ADS54J42 ovr_rng_indicatn_in_data_strm_sbas714.gif

Figure 67. Overrange Indication in a Data Stream

8.3.4.1 Fast OVR

The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented after only seven clock cycles, thus enabling a quicker reaction to an overrange event.

The input voltage level that the overload is detected at is referred to as the threshold. The threshold is programmable using the FOVR THRESHOLD bits, as shown in Figure 68. The FOVR is triggered seven output clock cycles after the overload condition occurs.

Figure 68. Programming Fast OVR Thresholds

The input voltage level that the fast OVR is triggered at is defined by Equation 2:

Equation 2. Full-Scale × [Decimal Value of the FOVR Threshold Bits] / 255)

The default threshold is E3h (227d), corresponding to a threshold of –1 dBFS.

In terms of full-scale input, the fast OVR threshold can be calculated as Equation 3:

Equation 3. 20log (FOVR Threshold / 255)

8.3.5 Power-Down Mode

The ADS54J42 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN pin or SPI register writes.

A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in Table 5. See the master page registers in Table 14 for further details.

Table 5. Register Addresses for Power-Down Modes

REGISTER ADDRESS	COMMENT	REGISTER DATA
A[7:0] (Hex)	COMMENT	7	6	5	4	3	2	1	0
MASTER PAGE (80h)
20	MASK 1	PDN ADC CHA				PDN ADC CHB
21	MASK 1	PDN BUFFER CHB		PDN BUFFER CHA		0	0	0	0
23	MASK 2	PDN ADC CHA				PDN ADC CHB
24	MASK 2	PDN BUFFER CHB		PDN BUFFER CHA		0	0	0	0
26	CONFIG	GLOBAL PDN	OVERRIDE PDN PIN	PDN MASK SEL	0	0	0	0	0
53		0	MASK SYSREF	0	0	0	0	0	0
55		0	0	0	PDN MASK	0	0	0	0

To save power, the device can be put in complete power-down by using the GLOBAL PDN register bit. However, when JESD is required to remain active when putting the device in power-down, the ADC and analog buffer can be powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 6 shows the power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx register bits.

Table 6. Power Consumption in Different Power-Down Settings

REGISTER BIT	COMMENT	I_AVDD3V (mA)	I_AVDD (mA)	I_DVDD (mA)	I_IOVDD (mA)	TOTAL POWER (W)
Default	After reset, with a full-scale input signal to both channels	247	260	137	382	1.94
GBL PDN = 1	The device is in a complete power-down state	3	6	23	192	0.28
GBL PDN = 0, PDN ADC CHx = 1 (x = A or B)	The ADC of one channel is powered down	206	166	97	367	1.54
GBL PDN = 0, PDN BUFF CHx = 1 (x = A or B)	The input buffer of one channel is powered down	195	258	137	381	1.78
GBL PDN = 0, PDN ADC CHx = 1, PDN BUFF CHx = 1 (x = A or B)	The ADC and input buffer of one channel are powered down	152	166	97	363	1.37
GBL PDN = 0, PDN ADC CHx = 1, PDN BUFF CHx = 1 (x = A and B)	The ADC and input buffer of both channels are powered down	55	70	56	356	0.81

8.4 Device Functional Modes

8.4.1 Device Configuration

The ADS54J42 can be configured by using a serial programming interface, as described in the Serial Interface section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down mode.

The ADS54J42 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Register Maps section) to access all register bits.

8.4.1.1 Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins, as shown in Figure 69. SPI bits in Figure 69 are explained in Table 7. Serially shifting bits into the device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can function with SCLK frequencies from 2 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

Figure 69. SPI Timing Diagram

Table 7. SPI Timing Diagram Legend

SPI BITS	DESCRIPTION	BIT SETTINGS
R/W	Read/write bit	0 = SPI write 1 = SPI read back
M	SPI bank access	0 = Analog SPI bank (master and ADC pages) 1 = JESD SPI bank (main digital, JESD analog, and JESD digital pages)
P	JESD page selection bit	0 = Page access 1 = Register access
CH	SPI access for a specific channel of the JESD SPI bank	0 = Channel A 1 = Channel B By default, both channels are being addressed.
A[11:0]	SPI address bits	—
D[7:0]	SPI data bits	—

Table 8 shows the timing requirements for the serial interface signals in Figure 69.

Table 8. SPI Timing Requirements

		MIN	MAX	UNIT
f_SCLK	SCLK frequency (equal to 1 / t_SCLK)	> dc	2	MHz
t_SLOADS	SEN to SCLK setup time	100		ns
t_SLOADH	SCLK to SEN hold time	100		ns
t_DSU	SDIN setup time	100		ns
t_DH	SDIN hold time	100		ns

8.4.1.2 Serial Register Write: Analog Bank

The analog SPI bank contains two pages (the master and ADC pages). The internal register of the ADS54J42 analog SPI bank can be programmed by:

Driving the SEN pin low.
Initiating a serial interface cycle specifying the page address of the register whose content must be written.
- Master page: write address 0011h with 80h.
- ADC page: write address 0011h with 0Fh.
Writing the register content as shown in Figure 70. When a page is selected, multiple writes into the same page can be done.

ADS54J42 srl_rgstr_write_tmng_dgm_sbas706.gif

Figure 70. Serial Register Write Timing Diagram

8.4.1.3 Serial Register Readout: Analog Bank

The content from one of the two analog banks can be read out by:

Driving the SEN pin low.
Selecting the page address of the register whose content must be read.
- Master page: write address 0011h with 80h.
- ADC page: write address 0011h with 0Fh.
Setting the R/W bit to 1 and writing the address to be read back.
Reading back the register content on the SDOUT pin, as shown in Figure 71. When a page is selected, multiple read backs from the same page can be done.

ADS54J42 srl_rgstr_read_tmng_dgm_sbas706.gif

Figure 71. Serial Register Read Timing Diagram

8.4.1.4 JESD Bank SPI Page Selection

The JESD SPI bank contains four pages (main digital, JESD digital, and JESD analog pages). The individual pages can be selected by:

Driving the SEN pin low.
Setting the M bit to 1 and specifying the page with two register writes. Note that the P bit must be set to 0, as shown in Figure 72.
- Write address 4003h with 00h (LSB byte of the page address).
- Write address 4004h with the MSB byte of the page address.
  - For the main digital page: write address 4004h with 68h.
  - For the JESD digital page: write address 4004h with 69h.
  - For the JESD analog page: write address 4004h with 6Ah.

Figure 72. SPI Page Selection

8.4.1.5 Serial Register Write: JESD Bank

The ADS54J42 is a dual-channel device and the JESD204B portion is configured individually for each channel by using the CH bit. Note that the P bit must be set to 1 for register writes.

Drive the SEN pin low.
Select the JESD bank page. Note that the M bit = 1 and the P bit = 0.
- Write address 4003h with 00h.
- Write address 4005h with 01h to enable separate control for both channels.
  - For the main digital page: write address 4004h with 68h.
  - For the JESD digital page: write address 4004h with 69h.
  - For the JESD analog page: write address 4004h with 6Ah.
Set the M and P bits to 1, select channel A (CH = 0) or channel B (CH = 1), and write the register content as shown in Figure 73. When a page is selected, multiple writes into the same page can be done.

ADS54J42 jesd_srl_rgstr_write_tmng_dgm_sbas706.gif

Figure 73. JESD Serial Register Write Timing Diagram

8.4.1.5.1 Individual Channel Programming

By default, register writes are applied to both channels. To enable individual channel writes, write address 4005h with 01h (default is 00h).

8.4.1.6 Serial Register Readout: JESD Bank

The content from one of the pages of the JESD bank can be read out by:

Driving the SEN pin low.
Selecting the JESD bank page. Note that the M bit = 1 and the P bit = 0.
- Write address 4003h with 00h.
- Write address 4005h with 01h to enable separate control for both channels.
  - For the main digital page: write address 4004h with 68h.
  - For the JESD digital page: write address 4004h with 69h.
  - For the JESD analog page: write address 4004h with 6Ah.
Setting the R/W, M, and P bits to 1, selecting channel A or channel B, and writing the address to be read back.
Reading back the register content on the SDOUT pin; see Figure 74. When a page is selected, multiple read backs from the same page can be done.

ADS54J42 jesd_srl_rgstr_read_tmng_dgm_sbas706.gif

Figure 74. JESD Serial Register Read Timing Diagram

8.4.2 JESD204B Interface

The ADS54J42 supports device subclass 1 with a maximum output data rate of 6.25 Gbps for each serial transmitter.

An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific sampling clock edge, allowing synchronization of multiple devices in a system and minimizing timing and alignment uncertainty. The SYNC input is used to control the JESD204B SERDES blocks.

Depending on the ADC output data rate, the JESD204B output interface can be operated with either two or four lanes per single ADC, as shown in Figure 75. The JESD204B setup and configuration of the frame assembly parameters is controlled via the SPI interface.

Figure 75. ADS54J42 Block Diagram

The JESD204B transmitter block shown in Figure 76 consists of the transport layer, the data scrambler, and the link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format. The link layer performs the 8b, 10b data encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data from the transport layer can be scrambled.

ADS54J42 jesd204b_trnsmttr_blck_sbas706.gif

Figure 76. JESD204B Transmitter Block

8.4.2.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started when the receiving device de-asserts the SYNC signal, as shown in Figure 77. When a logic low is detected on the SYNC input pin, the ADS54J42 starts transmitting comma (K28.5) characters to establish a code group synchronization.

When synchronization is complete, the receiving device asserts the SYNC signal and the ADS54J42 starts the initial lane alignment sequence with the next local multi-frame clock boundary. The ADS54J42 transmits four multi-frames, each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end symbols and the second multi-frame also contains the JESD204 link configuration data.

Figure 77. Lane Alignment Sequence

8.4.2.2 JESD204B Test Patterns

There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J42 supports a clock output, encoded, and a PRBS (2¹⁵ – 1) pattern. These test patterns can be enabled via an SPI register write and are located in the JESD digital page of the JESD bank.

8.4.2.3 JESD204B Frame

The JESD204B standard defines the following parameters:

L is the number of lanes per link.
M is the number of converters per device.
F is the number of octets per frame clock period, per lane.
S is the number of samples per frame per converter.

8.4.2.4 JESD204B Frame

Table 9 lists the available JESD204B formats and valid ranges for the ADS54J42 when the decimation filter is not used. The ranges are limited by the SERDES lane rate and the maximum ADC sample frequency.

NOTE

The 16-bit data going to the JESD 8b, 10b encoder is formed by padding two 0s as LSBs into the 14-bit ADC data.

Table 9. Default Interface Rates

L	M	F	S	DECIMATION	MINIMUM RATES		MAXIMUM RATES
L	M	F	S	DECIMATION	SAMPLING RATE (MSPS)	SERDES BIT RATE (Gbps)	SAMPLING RATE (MSPS)	SERDES BIT RATE (Gbps)
4	2	1	1	Not used	250	2.5	625	6.25
4	2	4	4	Not used	250	2.5	625	6.25
8	2	2	4	Not used	500	2.5	625	3.125

NOTE

In the LMFS = 8224 row of Table 9, the sample order in lane DA2 and DA3 are swapped.

The detailed frame assembly is shown in Table 10.

Table 10. Default Frame Assembly

PIN	LMFS = 4211	LMFS = 4244				LMFS = 8224
DA0						A₃[15:8]	A₃[7:0]
DA1	A₀[7:0]	A₂[15:8]	A₂[7:0]	A₃[15:8]	A₃[7:0]	A₂[15:8]	A₂[7:0]
DA2	A₀[15:8]	A₀[15:8]	A₀[7:0]	A₁[15:8]	A₁[7:0]	A₀[15:8]	A₀[7:0]
DA3						A₁[15:8]	A₁[7:0]
DB0						B₃[15:8]	B₃[7:0]
DB1	B₀[7:0]	B₂[15:8]	B₂[7:0]	B₃[15:8]	B₃[7:0]	B₂[15:8]	B₂[7:0]
DB2	B₀[15:8]	B₀[15:8]	B₀[7:0]	B₁[15:8]	B₁[7:0]	B₀[15:8]	B₀[7:0]
DB3						B₁[15:8]	B₁[7:0]

8.4.2.5 JESD204B Frame Assembly with Decimation

Table 11 lists the available JESD204B formats and valid ranges for the ADS54J42 when enabling the decimation filter. The ranges are limited by the SERDES lane rate (2.5 Gbps to 6.25 Gbps) and the ADC sample frequency (300 MSPS to 625 MSPS).

Table 11. Interface Rates with Decimation Filter

L	M	F	S	DECIMATION	MINIMUM RATES			MAXIMUM RATES
L	M	F	S	DECIMATION	DEVICE CLOCK FREQUENCY (MSPS)	OUTPUT SAMPLE RATE (MSPS)	SERDES BIT RATE (Gbps)	DEVICE CLOCK FREQUENCY (MSPS)	OUTPUT SAMPLE RATE (MSPS)	SERDES BIT RATE (Gbps)
4	4	2	1	4X (IQ)	500	125	2.5	625	156.25	3.125
4	2	2	2	2X	500	250	2.5	625	312.5	3.125
2	2	4	2	2X	300	150	3	625	312.5	6.25
2	2	2	1	4X	500	125	2.5	625	156.25	3.125
2	4	4	1	4X (IQ)	300	75	3	625	156.25	6.25
1	2	4	1	4X	300	75	3	625	156.25	6.25

Table 12 lists the detailed frame assembly with different decimation options.

Table 12. Frame Assembly with Decimation Filter

PIN	LMFS = 4222, 2X DECIMATION		LMFS = 2242, 2X DECIMATION				LMFS = 2221, 4X DECIMATION		LMFS = 2441, 4X DECIMATION (IQ)				LMFS = 4421, 4X DECIMATION (IQ)		LMFS = 1241, 4X DECIMATION
DA0	A1 [15:8]	A1 [7:0]											AQ0 [15:8]	AQ0 [7:0]
DA1	A0 [15:8]	A0 [7:0]	A0 [15:8]	A0 [7:0]	A1 [15:8]	A1 [7:0]	A0 [15:8]	A0 [7:0]	AI0 [15:8]	AI0 [7:0]	AQ0 [15:8]	AQ0 [7:0]	AI0 [15:8]	AI0 [7:0]	A0 [15:8]	A0 [7:0]	B0 [15:8]	B0 [7:0]
DA2
DA3
DB0	B1 [15:8]	B1 [7:0]											BQ0 [15:8]	BQ0 [7:0]
DB1	B0 [15:8]	B0 [7:0]	B0 [15:8]	B0 [7:0]	B1 [15:8]	B1 [7:0]	B0 [15:8]	B0 [7:0]	BI0 [15:8]	BI0 [7:0]	BQ0 [15:8]	BQ0 [7:0]	BI0 [15:8]	BI0 [7:0]
DB2
DB3

Appropriate register bits must be programmed to enable different options when the decimation filter is enabled. Table 13 summarizes all the decimation filter options available in the DDC block, the corresponding JESD link parameters (L, M, F, and S), and the register bits required to be programmed for each option.

Table 13. Program Summary of DDC Modes and JESD Link Configuration⁽¹⁾⁽²⁾

LMFS OPTIONS				DDC MODES PROGRAMMING				JESD LINK (LMFS) PROGRAMMING
L	M	F	S	DECIMATION OPTIONS	DEC MODE EN, DECFIL EN⁽³⁾	DECFIL MODE[3:0]⁽⁴⁾	JESD FILTER⁽⁵⁾	JESD MODE⁽⁶⁾	JESD PLL MODE⁽⁷⁾	LANE SHARE⁽⁸⁾	DA_BUS_ REORDER⁽⁹⁾	DB_BUS_ REORDER⁽¹⁰⁾	BUS_REORDER EN1⁽¹¹⁾	BUS_REORDER EN2⁽¹²⁾
4	2	1	1	No decimation	00	00	000	100	10	0	00h	00h	0	0
4	2	4	4	No decimation	00	00	000	010	10	0	00h	00h	0	0
8	2	2	4	No decimation (Default after reset)	00	00	000	001	00	0	00h	00h	0	0
4	4	2	1	4X (IQ)	11	0011 (LPF with f_S / 4 mixer)	111	001	00	0	0Ah	0Ah	1	1
4	2	2	2	2X	11	0010 (LPF) or 0110 (HPF)	110	001	00	0	0Ah	0Ah	1	1
2	2	4	2	2X	11	0010 (LPF) or 0110 (HPF)	110	010	10	0	0Ah	0Ah	1	1
2	2	2	1	4X	11	0000, 0100, 1000, or 1100 (all BPFs with different center frequencies).	100	001	00	0	0Ah	0Ah	1	1
2	4	4	1	4X (IQ)	11	0011 (LPF with an f_S / 4 mixer)	111	010	10	0	0Ah	0Ah	1	1
1	2	4	1	4X	11	0000, 0100, 1000, or 1100 (all BPFs with different center frequencies)	100	010	10	1	0Ah	0Ah	1	1

(1) Keeping the same LMFS settings for both channels is recommended.

(2) The PULSE RESET register bit must be pulsed after the registers in the main digital page are programmed.

(3) The DEC MODE EN and DECFIL EN register bits are located in the main digital page, register 04Dh (bit 3) and register 041h (bit 4).

(4) The DECFIL MODE[3:0] register bits are located in the main digital page, register 041h (bits 5 and 2-0).

(5) The JESD FILTER register bits are located in the JESD digital page, register 001h (bits 5-3).

(6) The JESD MODE register bits are located in the JESD digital page, register 001h (bits 2:0).

(7) The JESD PLL MODE register bits are located in the JESD analog page, register 016h (bits 1-0).

(8) The LANE SHARE register bit is located in the JESD digital page, register 016h (bit 4).

(9) The DA_BUS_REORDER register bits are located in the JESD digital page, register 031h (bits 7-0).

(10) The DB_BUS_REORDER register bits are located in the JESD digital page, register 032h (bits 7-0).

(11) The BUS_REORDER EN1 register bit is located in the main digital page, register 052h (bit 7).

(12) The BUS_REORDER EN2 register bit is located in the main digital page, register 072h (bit 3).

8.4.2.5.1 JESD Transmitter Interface

Each of the 6.25-Gbps SERDES JESD transmitter outputs requires ac-coupling between the transmitter and receiver. The differential pair must be terminated with 100-Ω resistors as close to the receiving device as possible to avoid unwanted reflections and signal degradation, as shown in Figure 78.

Figure 78. Output Connection to Receiver

8.4.2.5.2 Eye Diagrams

Figure 79 and Figure 80 show the serial output eye diagrams of the ADS54J42 at 6.25 Gbps and 2.5 Gbps (respectively) with default output voltage swings against the JESD204B mask.

ADS54J42 default_6.25gbps_eye_dgm_sbas756.png

Figure 79. Eye Diagram at 6.25-Gbps Bit Rate with
Default Output Swing

ADS54J42 default_2.5gbps_eye_dgm_sbas756.png

Figure 80. Eye Diagram at 2.5-Gbps Bit Rate with
Default Output Swing

8.5 Register Maps

Figure 81 shows a conceptual diagram of the serial registers.

ADS54J42 serial_intrfc_rgstrs_sbas756.gif

Figure 81. Serial Interface Registers

8.5.1 Detailed Register Info

The ADS54J42 contains two main SPI banks. The analog SPI bank provides access to the ADC analog blocks and the digital SPI bank controls the interleaving engine and anything related to the JESD204B serial interface. The analog SPI bank is divided into two pages (master and ADC) and the digital SPI bank is divided into three pages (main digital, JESD digital, and JESD analog). Table 14 lists a register map for the ADS54J42.

Table 14. Register Map

REGISTER ADDRESS	REGISTER DATA
A[11:0] (Hex)	7	6	5	4	3	2	1	0
GENERAL REGISTERS
0	RESET	0	0	0	0	0	0	RESET
3	JESD BANK PAGE SEL[7:0]
4	JESD BANK PAGE SEL[15:8]
5	0	0	0	0	0	0	0	DISABLE BROADCAST
11	ANALOG BANK PAGE SEL
MASTER PAGE (80h)
20	PDN ADC CHA				PDN ADC CHB
21	PDN BUFFER CHB		PDN BUFFER CHA		0	0	0	0
23	PDN ADC CHA				PDN ADC CHB
24	PDN BUFFER CHB		PDN BUFFER CHA		0	0	0	0
26	GLOBAL PDN	OVERRIDE PDN PIN	PDN MASK SEL	0	0	0	0	0
39	HIGH FREQ 1	HIGH FREQ 0	0	0	0	0	0	0
3A	0	HIGH FREQ 2	0	0	0	0	0	0
4F	0	0	0	0	0	0	0	EN INPUT DC COUPLING
53	0	MASK SYSREF	0	0	0	0	EN SYSREF DC COUPLING	0
55	0	0	0	PDN MASK	0	0	0	0
56	0	0	0	0	0	HIGH FREQ 3	0	0
59	FOVR CHB	0	ALWAYS WRITE 1	0	0	0	0	0
ADC PAGE (0Fh)
5F	FOVR THRESHOLD PROG
MAIN DIGITAL PAGE (6800h)
0	0	0	0	0	0	0	0	PULSE RESET
41	0	0	DECFIL MODE[3]	DECFIL EN	0	DECFIL MODE[2:0]
42	0	0	0	0	0	NYQUIST ZONE
43	0	0	0	0	0	0	0	FORMAT SEL
44	0	DIGITAL GAIN
4B	0	0	FORMAT EN	0	0	0	0	0
4D	0	0	0	0	DEC MODE EN	0	0	0
4E	CTRL NYQUIST	0	0	0	0	0	0	0
52	BUS_ REORDER EN1	0	0	0	0	0	0	DIG GAIN EN
72	0	0	0	0	BUS_ REORDER EN2	0	0	0
AB	0	0	0	0	0	0	0	LSB SEL EN
AD	0	0	0	0	0	0	LSB SELECT
F7	0	0	0	0	0	0	0	DIG RESET
JESD DIGITAL PAGE (6900h)
0	CTRL K	0	0	TESTMODE EN	FLIP ADC DATA	LANE ALIGN	FRAME ALIGN	TX LINK DIS
1	SYNC REG	SYNC REG EN	JESD FILTER			JESD MODE
2	LINK LAYER TESTMODE			LINK LAYER RPAT	LMFC MASK RESET	0	0	0
3	FORCE LMFC COUNT	LMFC COUNT INIT					RELEASE ILANE SEQ
5	SCRAMBLE EN	0	0	0	0	0	0	0
6	0	0	0	FRAMES PER MULTI FRAME (K)
7	0	0	0	0	SUBCLASS	0	0	0
16	1	0	0	LANE SHARE	0	0	0	0
31	DA_BUS_REORDER[7:0]
32	DB_BUS_REORDER[7:0]
JESD ANALOG PAGE (6A00h)
12	SEL EMP LANE 1						0	0
13	SEL EMP LANE 0						0	0
14	SEL EMP LANE 2						0	0
15	SEL EMP LANE 3						0	0
16	0	0	0	0	0	0	JESD PLL MODE
17	0	PLL RESET	0	0	0	0	0	0
1A	0	0	0	0	0	0	FOVR CHA	0
1B	JESD SWING			0	FOVR CHA EN	0	0	0

8.5.2 Example Register Writes

This section provides three different example register writes. Table 15 describes a global power-down register write, Table 16 describes the register writes when the default lane setting (eight active lanes per device) is changed to four active lanes (LMFS = 4211), and Table 17 describes the register writes for 2X decimation with four active lanes (LMFS = 4222).

Table 15. Global Power Down

ADDRESS (Hex)	DATA (Hex)	COMMENT
0-011h	80h	Set the master page
0-026h	C0h	Set the global power-down

Table 16. Two Lanes per Channel Mode (LMFS = 4211)

ADDRESS (Hex)	DATA (Hex)	COMMENT
4-004h	69h	Select the JESD digital page
4-003h	00h	Select the JESD digital page
6-001h	02h	Select the digital to 40X mode
4-004h	6Ah	Select the JESD analog page
6-016h	02h	Set the SERDES PLL to 40X mode

Table 17. 2X Decimation (LPF for Both Channels) with Four Active Lanes (LMFS = 4222)

ADDRESS (Hex)	DATA (Hex)	COMMENT
4-004h	68h	Select the main digital page (6800h)
4-003h	00h	Select the main digital page (6800h)
6-041h	12h	Set decimate-by-2 (low-pass filter)
6-04Dh	08h	Enable decimation filter control
6-072h	08h	BUS_REORDER EN2
6-052h	80h	BUS_REORDER EN1
6-000h	01h	Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect).
6-000h	00h
4-004h	69h	Select the JESD digital page (6900h)
4-003h	00h	Select the JESD digital page (6900h)
6-031h	0Ah	Output bus reorder for channel A
6-032h	0Ah	Output bus reorder for channel B
6-001h	31h	Program the JESD MODE and JESD FILTER register bits for LMFS = 4222.

8.5.3 Register Descriptions

8.5.3.1 General Registers

8.5.3.1.1 Register 0h (address = 0h)

Figure 82. Register 0h

7	6	5	4	3	2	1	0
RESET	0	0	0	0	0	0	RESET
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: W = Write only; -n = value after reset

Table 18. Register 0h Field Descriptions

Bit	Field	Type	Reset	Description
7	RESET	W	0h	0 = Normal operation 1 = Internal software reset, clears back to 0
6-1	0	W	0h	Must write 0
0	RESET	W	0h	0 = Normal operation 1 = Internal software reset, clears back to 0

8.5.3.1.2 Register 3h (address = 3h)

Figure 83. Register 3h

7	6	5	4	3	2	1	0
JESD BANK PAGE SEL[7:0]
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 19. Register 3h Field Descriptions

Bit	Field	Type	Reset	Description
7-0	JESD BANK PAGE SEL[7:0]	R/W	0h	Program these bits to access the desired page in the JESD bank. 6800h = Main digital page selected 6900h = JESD digital page selected 6A00h = JESD analog page selected

8.5.3.1.3 Register 4h (address = 4h)

Figure 84. Register 4h

7	6	5	4	3	2	1	0
JESD BANK PAGE SEL[15:8]
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 20. Register 4h Field Descriptions

Bit	Field	Type	Reset	Description
7-0	JESD BANK PAGE SEL[15:8]	R/W	0h	Program these bits to access the desired page in the JESD bank. 6800h = Main digital page selected 6900h = JESD digital page selected 6A00h = JESD analog page selected

8.5.3.1.4 Register 5h (address = 5h)

Figure 85. Register 5h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	DISABLE BROADCAST
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 21. Register 5h Field Descriptions

Bit	Field	Type	Reset	Description
7-1	0	W	0h	Must write 0
0	DISABLE BROADCAST	R/W	0h	0 = Normal operation; channel A and B are programmed as a pair 1 = Channel A and B can be individually programmed based on the CH bit

8.5.3.1.5 Register 11h (address = 11h)

Figure 86. Register 11h

7	6	5	4	3	2	1	0
ANALOG PAGE SELECTION
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 22. Register 11h Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ANALOG BANK PAGE SEL	R/W	0h	Program these bits to access the desired page in the analog bank. Master page = 80h ADC page = 0Fh

8.5.3.2 Master Page (080h) Registers

8.5.3.2.1 Register 20h (address = 20h), Master Page (080h)

Figure 87. Register 20h

7	6	5	4	3	2	1	0
PDN ADC CHA				PDN ADC CHB
R/W-0h				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 23. Registers 20h Field Descriptions

Bit	Field	Type	Reset	Description
7-4	PDN ADC CHA	R/W	0h	There are two power-down masks that are controlled via the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register bit 5 in address 26h. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h.
3-0	PDN ADC CHB	R/W	0h

8.5.3.2.2 Register 21h (address = 21h), Master Page (080h)

Figure 88. Register 21h

7	6	5	4	3	2	1	0
PDN BUFFER CHB		PDN BUFFER CHA		0	0	0	0
R/W-0h		R/W-0h		W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 24. Register 21h Field Descriptions

Bit	Field	Type	Reset	Description
7-6	PDN BUFFER CHB	R/W	0h	There are two power-down masks that are controlled via the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register address 26h, bit 5. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h.
5-4	PDN BUFFER CHA	R/W	0h
3-0	0	W	0h	Must write 0.

8.5.3.2.3 Register 23h (address = 23h), Master Page (080h)

Figure 89. Register 23h

7	6	5	4	3	2	1	0
PDN ADC CHA				PDN ADC CHB
R/W-0h				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 25. Register 23h Field Descriptions

Bit	Field	Type	Reset	Description
7-4	PDN ADC CHA	R/W	0h	There are two power-down masks that are controlled via the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register address 26h, bit 5. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h.
3-0	PDN ADC CHB	R/W	0h

8.5.3.2.4 Register 24h (address = 24h), Master Page (080h)

Figure 90. Register 24h

7	6	5	4	3	2	1	0
PDN BUFFER CHB		PDN BUFFER CHA		0	0	0	0
R/W-0h		R/W-0h		W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 26. Register 24h Field Descriptions

Bit	Field	Type	Reset	Description
7-6	PDN BUFFER CHB	R/W	0h	There are two power-down masks that are controlled via the PDN mask register bit in address 55h. The power-down mask 1 or mask 2 are selected via register address 26h, bit 5. Power-down mask 1: addresses 20h and 21h. Power-down mask 2: addresses 23h and 24h.
5-4	PDN BUFFER CHA	R/W	0h
3-0	0	W	0h	Must write 0.

8.5.3.2.5 Register 26h (address = 26h), Master Page (080h)

Figure 91. Register 26h

7	6	5	4	3	2	1	0
GLOBAL PDN	OVERRIDE PDN PIN	PDN MASK SEL	0	0	0	0	0
R/W-0h	R/W-0h	R/W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 27. Register 26h Field Descriptions

Bit	Field	Type	Reset	Description
7	GLOBAL PDN	R/W	0h	Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be programmed. 0 = Normal operation 1 = Global power-down via the SPI
6	OVERRIDE PDN PIN	R/W	0h	This bit ignores the power-down pin control. 0 = Normal operation 1 = Ignores inputs on the power-down pin
5	PDN MASK SEL	R/W	0h	This bit selects power-down mask 1 or mask 2. 0 = Power-down mask 1 1 = Power-down mask 2
4-0	0	W	0h	Must write 0

8.5.3.2.6 Register 39h (address = 39h), Master Page (080h)

Figure 92. Register 39h

7	6	5	4	3	2	1	0
HIGH FREQ 1	HIGH FREQ 0	0	0	0	0	0	0
R/W-0h	R/W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 28. Register 39h Field Descriptions

Bit	Field	Type	Reset	Description
7	HIGH FREQ 1	R/W	0h	Set these bits (and the HIGH FREQ[3:2] bits) high when the input frequency > 400 MHz.
6	HIGH FREQ 0	R/W	0h
5-0	0	W	0h	Must write 0

8.5.3.2.7 Register 3Ah (address = 3Ah), Master Page (080h)

Figure 93. Register 3Ah

7	6	5	4	3	2	1	0
0	HIGH FREQ 2	0	0	0	0	0	0
W-0h	R/W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 29. Register 3Ah Field Descriptions

Bit	Field	Type	Reset	Description
7	0	W	0h	Must write 0
6	HIGH FREQ 2	R/W	0h	Set this bit (and the HIGH FREQ 3 and HIGH FREQ[1:0] bits) high when the input frequency > 400 MHz.
5-0	0	W	0h	Must write 0

8.5.3.2.8 Register 4Fh (address = 4Fh), Master Page (080h)

Figure 94. Register 4Fh

7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	EN INPUT DC COUPLING
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 30. Register 4Fh Field Descriptions

Bit	Field	Type	Reset	Description
7-1	0	W	0h	Must write 0
0	EN INPUT DC COUPLING	R/W	0h	This bit enables dc-coupling between the analog inputs and the driver by changing the internal biasing resistor between the analog inputs and VCM from 600 Ω to 5 kΩ. 0 = The dc-coupling support is disabled 1 = The dc-coupling support is enabled

8.5.3.2.9 Register 53h (address = 53h), Master Page (080h)

Figure 95. Register 53h

7	6	5	4	3	2	1	0
0	MASK SYSREF	0	0	0	0	EN SYSREF DC COUPLING	0
W-0h	R/W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 31. Register 53h Field Descriptions

Bit	Field	Type	Reset	Description
7	0	W	0h	Must write 0
6	MASK SYSREF	R/W	0h	0 = Normal operation 1 = Ignores the SYSREF input
5-2	0	W	0h	Must write 0
1	EN SYSREF DC COUPLING	R/W	0h	This bit enables a higher common-mode voltage input on the SYSREF signal (up to 1.6 V). 0 = Normal operation 1 = Enables a higher SYSREF common-mode voltage support
0	0	W	0h	Must write 0

8.5.3.2.10 Register 55h (address = 55h), Master Page (080h)

Figure 96. Register 55h

7	6	5	4	3	2	1	0
0	0	0	PDN MASK	0	0	0	0
W-0h	W-0h	W-0h	R/W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 32. Register 55h Field Descriptions

Bit	Field	Type	Reset	Description
7-5	0	W	0h	Must write 0
4	PDN MASK	R/W	0h	This bit enables power-down via a register bit. 0 = Normal operation 1 = Power-down is enabled by powering down the internal blocks as specified in the selected power-down mask
3-0	0	W	0h	Must write 0

8.5.3.2.11 Register 56h (address = 56h), Master Page (080h)

Figure 97. Register 56h

7	6	5	4	3	2	1	0
0	0	0	0	0	HIGH FREQ 3	0	0
W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 33. Register 56h Field Descriptions

Bit	Field	Type	Reset	Description
7-3	0	W	0h	Must write 0
2	HIGH FREQ 3	R/W	0h	Set this bit (and the HIGH FREQ[2:0] bits) high when the input frequency > 400 MHz.
1-0	0	W	0h	Must write 0

8.5.3.2.12 Register 59h (address = 59h), Master Page (080h)

Figure 98. Register 59h

7	6	5	4	3	2	1	0
FOVR CHB	0	ALWAYS WRITE 1	0	0	0	0	0
W-0h	W-0h	R/W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 34. Register 59h Field Descriptions

Bit	Field	Type	Reset	Description
7	FOVR CHB	W	0h	This bit outputs the FOVR signal for channel B on the SDOUT pin. 0 = Normal operation 1 = The FOVR signal is available on the SDOUT pin
6	0	W	0h	Must write 0
5	ALWAYS WRITE 1	R/W	0h	Must write 1
4-0	0	W	0h	Must write 0

8.5.3.3 ADC Page (0Fh) Register

8.5.3.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)

Figure 99. Register 5F

7	6	5	4	3	2	1	0
FOVR THRESHOLD PROG
R/W-E3h

LEGEND: R/W = Read/Write; -n = value after reset

Table 35. Register 5F Field Descriptions

Bit	Field	Type	Reset	Description
7-0	FOVR THRESHOLD PROG	R/W	E3h	Program the fast OVR thresholds together for channel A and B, as described in the Overrange Indication section.

8.5.3.4 Main Digital Page (6800h) Registers

8.5.3.4.1 Register 0h (address = 0h), Main Digital Page (6800h)

Figure 100. Register 0h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	PULSE RESET
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 36. Register 0h Field Descriptions

Bit	Field	Type	Reset	Description
7-1	0	W	0h	Must write 0
0	PULSE RESET	R/W	0h	This bit must be pulsed after power-up or after configuring registers in the main digital page of the JESD bank. Any register bits in the main digital page (6800h) take effect only after this bit is pulsed; see the Start-Up Sequence section for the correct sequence. 0 = Normal operation 0 → 1 → 0 = This bit is pulsed

8.5.3.4.2 Register 41h (address = 41h), Main Digital Page (6800h)

Figure 101. Register 41h

7	6	5	4	3	2	1	0
0	0	DECFIL MODE[3]	DECFIL EN	0	DECFIL MODE[2:0]
W-0h	W-0h	R/W-0h	R/W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 37. Register 41h Field Descriptions

Bit	Field	Type	Reset	Description
7-6	0	W	0h	Must write 0
5	DECFIL MODE[3]	R/W	0h	This bit selects the decimation filter mode. Table 38 lists the bit settings. The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and decimation filter enable (DECFIL EN, register 41h, bit 4) must be enabled.
4	DECFIL EN	R/W	0h	This bit enables the digital decimation filter. 0 = Normal operation, full rate output 1 = Digital decimation enabled
3	0	W	0h	Must write 0
2-0	DECFIL MODE[2:0]	R/W	0h	These bits select the decimation filter mode. Table 38 lists the bit settings. The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and decimation filter enable (DECFIL EN, register 41h, bit 4) must be enabled.

Table 38. DECFIL MODE Bit Settings

BITS (5, 2-0)	FILTER MODE	DECIMATION
0000	Band-pass filter centered on 3 × f_S / 16	4X
0100	Band-pass filter centered on 5 × f_S / 16	4X
1000	Band-pass filter centered on 1 × f_S / 16	4X
1100	Band-pass filter centered on 7 × f_S / 16	4X
0010	Low-pass filter	2X
0110	High-pass filter	2X
0011	Low-pass filter with f_S / 4 mixer	4X (IQ)

8.5.3.4.3 Register 42h (address = 42h), Main Digital Page (6800h)

Figure 102. Register 42h

7	6	5	4	3	2	1	0
0	0	0	0	0	NYQUIST ZONE
W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 39. Register 42h Field Descriptions

Bit	Field	Type	Reset	Description
7-3	0	W	0h	Must write 0
2-0	NYQUIST ZONE	R/W	0h	The Nyquist zone must be selected for proper interleaving correction. Nyquist refers to the device clock / 2. For a 625-MSPS device clock, the Nyquist frequency is 312.5 MHz. The CTRL NYQUIST register bit (register 4Eh, bit 7) must also be set. 000 = First Nyquist zone (0 MHz to 312.5 MHz) 001 = Second Nyquist zone (312.5 MHz to 625 MHz) 010 = Third Nyquist zone (625 MHz to 937.5 MHz) All others = Not used

8.5.3.4.4 Register 43h (address = 43h), Main Digital Page (6800h)

Figure 103. Register 43h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	FORMAT SEL
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 40. Register 43h Field Descriptions

Bit	Field	Type	Reset	Description
7-1	0	W	0h	Must write 0
0	FORMAT SEL	R/W	0h	This bit changes the output format. Set the FORMAT EN bit to enable control using this bit. 0 = Twos complement 1 = Offset binary

8.5.3.4.5 Register 44h (address = 44h), Main Digital Page (6800h)

Figure 104. Register 44h

7	6	5	4	3	2	1	0
0	DIGITAL GAIN
R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 41. Register 44h Field Descriptions

Bit	Field	Type	Reset	Description
7	0	R/W	0h	Must write 0
6-0	DIGITAL GAIN	R/W	0h	These bits set the digital gain setting. The DIG GAIN EN register bit (register 52h, bit 0) must be enabled to use these bits. Gain in dB = 20log (digital gain / 32). 7Fh = 127 equals a digital gain of 9.5 dB.

8.5.3.4.6 Register 4Bh (address = 4Bh), Main Digital Page (6800h)

Figure 105. Register 4Bh

7	6	5	4	3	2	1	0
0	0	FORMAT EN	0	0	0	0	0
W-0h	W-0h	R/W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 42. Register 4Bh Field Descriptions

Bit	Field	Type	Reset	Description
7-6	0	W	0h	Must write 0
5	FORMAT EN	R/W	0h	This bit enables control for data format selection using the FORMAT SEL register bit. 0 = Default, output is in twos complement format 1 = Output is in offset binary format after the FORMAT SEL bit is set
4-0	0	W	0h	Must write 0

8.5.3.4.7 Register 4Dh (address = 4Dh), Main Digital Page (6800h)

Figure 106. Register 4Dh

7	6	5	4	3	2	1	0
0	0	0	0	DEC MOD EN	0	0	0
W-0h	W-0h	W-0h	W-0h	R/W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 43. Register 4Dh Field Descriptions

Bit	Field	Type	Reset	Description
7-4	0	W	0h	Must write 0
3	DEC MOD EN	R/W	0h	This bit enables control of the decimation filter mode via the DECFIL MODE[3:0] register bits. 0 = Default 1 = Decimation mode control is enabled
2-0	0	W	0h	Must write 0

8.5.3.4.8 Register 4Eh (address = 4Eh), Main Digital Page (6800h)

Figure 107. Register 4Eh

7	6	5	4	3	2	1	0
CTRL NYQUIST	0	0	0	0	0	0	0
R/W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 44. Register 4Eh Field Descriptions

Bit	Field	Type	Reset	Description
7	CTRL NYQUIST	R/W	0h	This bit enables selecting the Nyquist zone using register 42h, bits 2-0. 0 = Selection disabled 1 = Selection enabled
6-0	0	W	0h	Must write 0

8.5.3.4.9 Register 52h (address = 52h), Main Digital Page (6800h)

Figure 108. Register 52h

7	6	5	4	3	2	1	0
BUS_REORDER EN1	0	0	0	0	0	0	DIG GAIN EN
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 45. Register 52h Field Descriptions

Bit	Field	Type	Reset	Description
7	BUS_REORDER EN1	R/W	0h	Must write 1 in DDC mode only.
6-1	0	W	0h	Must write 0
0	DIG GAIN EN	R/W	0h	This bit enables selecting the digital gain for register 44h. 0 = Digital gain disabled 1 = Digital gain enabled

8.5.3.4.10 Register 72h (address = 72h), Main Digital Page (6800h)

Figure 109. Register 72h

7	6	5	4	3	2	1	0
0	0	0	0	BUS_REORDER EN2	0	0	0
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 46. Register 72h Field Descriptions

Bit	Field	Type	Reset	Description
7-4	0	W	0h	Must write 0
3	BUS_REORDER EN2	R/W	0h	Must write 1 in DDC mode only.
2-0	0	W	0h	Must write 0

8.5.3.4.11 Register ABh (address = ABh), Main Digital Page (6800h)

Figure 110. Register ABh

7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	LSB SEL EN
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 47. Register ABh Field Descriptions

Bit	Field	Type	Reset	Description
7-1	0	W	0h	Must write 0
0	LSB SEL EN	R/W	0h	This bit enables control for the LSB SELECT register bit. 0 = Default 1 = LSB of the 16-bit data (14-bit ADC data padded with two 0s as the LSBs) can be programmed as fast OVR using the LSB SELECT register bit.

8.5.3.4.12 Register ADh (address = ADh), Main Digital Page (6800h)

Figure 111. Register ADh

7	6	5	4	3	2	1	0
0	0	0	0	0	0	LSB SELECT
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 48. Register ADh Field Descriptions

Bit	Field	Type	Reset	Description
7-2	0	W	0h	Must write 0
1-0	LSB SELECT	R/W	0h	These bits enable the output of the FOVR flag instead of the output data LSB. Ensure that the LSB SEL EN register bit is set to 1. 00 = Output is 16-bit data (14-bit ADC data padded with two 0s as the LSBs) 11 = The LSB of the 16-bit output data is replaced by the FOVR information for each channel

8.5.3.4.13 Register F7h (address = F7h), Main Digital Page (6800h)

Figure 112. Register F7h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	DIG RESET
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: W = Write only; -n = value after reset

Table 49. Register F7h Field Descriptions

Bit	Field	Type	Reset	Description
7-1	0	W	0h	Must write 0
0	DIG RESET	W	0h	This bit is the self-clearing reset for the digital block and does not include interleaving correction. 0 = Normal operation 1 = Digital reset

8.5.3.5 JESD Digital Page (6900h) Registers

8.5.3.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)

Figure 113. Register 0h

7	6	5	4	3	2	1	0
CTRL K	0	0	TESTMODE EN	FLIP ADC DATA	LANE ALIGN	FRAME ALIGN	TX LINK DIS
R/W-0h	W-0h	W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 50. Register 0h Field Descriptions

Bit	Field	Type	Reset	Description
7	CTRL K	R/W	0h	This bit is the enable bit for a number of frames per multi-frame. 0 = Default is five frames per multi-frame 1 = Frames per multi-frame can be set in register 06h
6-5	0	W	0h	Must write 0
4	TESTMODE EN	R/W	0h	This bit generates the long transport layer test pattern mode, as per section 5.1.6.3 of the JESD204B specification. 0 = Test mode disabled 1 = Test mode enabled
3	FLIP ADC DATA	R/W	0h	0 = Normal operation 1 = Output data order is reversed: MSB to LSB.
2	LANE ALIGN	R/W	0h	This bit inserts the lane alignment character (K28.3) for the receiver to align to the lane boundary, as per section 5.3.3.5 of the JESD204B specification. 0 = Normal operation 1 = Inserts lane alignment characters
1	FRAME ALIGN	R/W	0h	This bit inserts the lane alignment character (K28.7) for the receiver to align to the lane boundary, as per section 5.3.3.5 of the JESD204B specification. 0 = Normal operation 1 = Inserts frame alignment characters
0	TX LINK DIS	R/W	0h	This bit disables sending the initial link alignment (ILA) sequence when SYNC is de-asserted. 0 = Normal operation 1 = ILA disabled

8.5.3.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)

Figure 114. Register 1h

7	6	5	4	3	2	1	0
SYNC REG	SYNC REG EN	JESD FILTER			JESD MODE
R/W-0h	R/W-0h	R/W-0h			R/W-01h

LEGEND: R/W = Read/Write; -n = value after reset

Table 51. Register 1h Field Descriptions

Bit	Field	Type	Reset	Description
7	SYNC REG	R/W	0h	This bit is the register control for the sync request. 0 = Normal operation 1 = ADC output data are replaced with K28.5 characters; the SYNC REG EN register bit must also be set to 1
6	SYNC REG EN	R/W	0h	This bit enables register control for the sync request. 0 = Use the SYNC pin for sync requests 1 = Use the SYNC REG register bit for sync requests
5-3	JESD FILTER	R/W	0h	These bits and the JESD MODE bits set the correct LMFS configuration for the JESD interface. The JESD FILTER setting must match the configuration in the decimation filter page. 000 = Filter bypass mode See Table 52 for valid combinations for register bits JESD FILTER along with JESD MODE.
2-0	JESD MODE	R/W	01h	These bits select the number of serial JESD output lanes per ADC. The JESD PLL MODE register bit located in the JESD analog page must also be set accordingly. 001 = Default after reset(Eight active lanes) See Table 52 for valid combinations for register bits JESD FILTER along with JESD MODE.

Table 52. Valid Combinations for JESD FILTER and JESD MODE Bits

REGISTER BIT JESD FILTER	REGISTER BIT JESD MODE	DECIMATION FACTOR	NUMBER OF ACTIVE LANES PER DEVICE
000	100	No decimation	Four lanes are active
000	010	No decimation	Four lanes are active
000	001	No decimation (default after reset)	Eight lanes are active
111	001	4X (IQ)	Four lanes are active
110	001	2X	Four lanes are active
110	010	2X	Two lanes are active
100	001	4X	Two lanes are active
111	010	4X (IQ)	Two lanes are active
100	010	4X	One lane is active

8.5.3.5.3 Register 2h (address = 2h), JESD Digital Page (6900h)

Figure 115. Register 2h

7	6	5	4	3	2	1	0
LINK LAYER TESTMODE			LINK LAYER RPAT	LMFC MASK RESET	0	0	0
R/W-0h			R/W-0h	R/W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 53. Register 2h Field Descriptions

Bit	Field	Type	Reset	Description
7-5	LINK LAYER TESTMODE	R/W	0h	These bits generate a pattern as per section 5.3.3.8.2 of the JESD204B document. 000 = Normal ADC data 001 = D21.5 (high-frequency jitter pattern) 010 = K28.5 (mixed-frequency jitter pattern) 011 = Repeat initial lane alignment (generates a K28.5 character and continuously repeats lane alignment sequences) 100 = 12-octet RPAT jitter pattern All others = Not used
4	LINK LAYER RPAT	R/W	0h	This bit changes the running disparity in the modified RPAT pattern test mode (only when the link layer test mode = 100). 0 = Normal operation 1 = Changes disparity
3	LMFC MASK RESET	R/W	0h	This bit masks the LMFC reset coming to the digital block. 0 = LMFC reset is not masked 1 = Ignore the LMFC reset request
2-0	0	W	0h	Must write 0

8.5.3.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)

Figure 116. Register 3h

7	6	5	4	3	2	1	0
FORCE LMFC COUNT	LMFC COUNT INIT					RELEASE ILANE SEQ
R/W-0h	R/W-0h					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 54. Register 3h Field Descriptions

Bit	Field	Type	Reset	Description
7	FORCE LMFC COUNT	R/W	0h	This bit forces the LMFC count. 0 = Normal operation 1 = Enables using a different starting value for the LMFC counter
6-2	MASK SYSREF	R/W	0h	When SYSREF transmits to the digital block, the LMFC count resets to 0 and K28.5 stops transmitting when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using LMFC COUNT INIT. In this manner, the receiver can be synchronized early because the LANE ALIGNMENT SEQUENCE is received early. The FORCE LMFC COUNT register bit must be enabled.
1-0	RELEASE ILANE SEQ	R/W	0h	These bits delay the generation of the lane alignment sequence by 0, 1, 2, or 3 multi-frames after the code group synchronization. 00 = 0 01 = 1 10 = 2 11 = 3

8.5.3.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)

Figure 117. Register 5h

7	6	5	4	3	2	1	0
SCRAMBLE EN	0	0	0	0	0	0	0
R/W-Undefined	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 55. Register 5h Field Descriptions

Bit	Field	Type	Reset	Description
7	SCRAMBLE EN	R/W	Undefined	This bit is the scramble enable bit in the JESD204B interface. 0 = Scrambling disabled 1 = Scrambling enabled
6-0	0	W	0h	Must write 0

8.5.3.5.6 Register 6h (address = 6h), JESD Digital Page (6900h)

Figure 118. Register 6h

7	6	5	4	3	2	1	0
0	0	0	FRAMES PER MULTI FRAME (K)
W-0h	W-0h	W-0h	R/W-8h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 56. Register 6h Field Descriptions

Bit	Field	Type	Reset	Description
7-5	0	W	0h	Must write 0
4-0	FRAMES PER MULTI FRAME (K)	R/W	8h	These bits set the number of multi-frames. Actual K is the value in hex + 1 (that is, 0Fh is K = 16).

8.5.3.5.7 Register 7h (address = 7h), JESD Digital Page (6900h)

Figure 119. Register 7h

7	6	5	4	3	2	1	0
0	0	0	0	SUBCLASS	0	0	0
W-0h	W-0h	W-0h	W-0h	R/W-1h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 57. Register 7h Field Descriptions

Bit	Field	Type	Reset	Description
7-4	0	W	0h	Must write 0
3	SUBCLASS	R/W	1h	This bit sets the JESD204B subclass. 000 = Subclass 0 is backward compatible with JESD204A 001 = Subclass 1 deterministic latency using the SYSREF signal
2-0	0	W	0h	Must write 0

8.5.3.5.8 Register 16h (address = 16h), JESD Digital Page (6900h)

Figure 120. Register 16h

7	6	5	4	3	2	1	0
1	0	0	LANE SHARE	0	0	0	0
W-1h	W-0h	R/W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 58. Register 16h Field Descriptions

Bit	Field	Type	Reset	Description
7	1	W	1h	Must write 1
6-5	0	W	0h	Must write 0
4	LANE SHARE	R/W	0h	When using decimate-by-4, the data of both channels are output over one lane (LMFS = 1241). 0 = Normal operation (each channel uses one lane) 1 = Lane sharing is enabled, both channels share one lane (LMFS = 1241)
3-0	0	W	0h	Must write 0

8.5.3.5.9 Register 31h (address = 31h), JESD Digital Page (6900h)

Figure 121. Register 31h

7	6	5	4	3	2	1	0
DA_BUS_REORDER[7:0]
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 59. Register 31h Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DA_BUS_REORDER[7:0]	R/W	0h	Use these bits to program output connections between data streams and output lanes in decimate-by-2 and decimate-by-4 mode. Table 13 lists the supported combinations of these bits.

8.5.3.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)

Figure 122. Register 32h

7	6	5	4	3	2	1	0
DB_BUS_REORDER[7:0]
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 60. Register 32h Field Descriptions

Bit	Field	Type	Reset	Description
7-0	DB_BUS_REORDER[7:0]	R/W	0h	Use these bits to program output connections between data streams and output lanes in decimate-by-2 and decimate-by-4 mode. Table 13 lists the supported combinations of these bits.

8.5.3.6 JESD Analog Page (6A00h) Registers

8.5.3.6.1 Registers 12h-5h (addresses = 12h-5h), JESD Analog Page (6A00h)

Figure 123. Register 12h

7	6	5	4	3	2	1	0
SEL EMP LANE 1						0	0
R/W-0h						W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Figure 124. Register 13h

7	6	5	4	3	2	1	0
SEL EMP LANE 0						0	0
R/W-0h						W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Figure 125. Register 14h

7	6	5	4	3	2	1	0
SEL EMP LANE 2						0	0
R/W-0h						W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Figure 126. Register 15h

7	6	5	4	3	2	1	0
SEL EMP LANE 3						0	0
R/W-0h						W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 61. Registers 12h-15h Field Descriptions

Bit	Field	Type	Reset	Description
7-2	SEL EMP LANE x (where x = 1, 0, 2, or 3)	R/W	0h	These bits select the amount of de-emphasis for the JESD output transmitter. The de-emphasis value in decibels (dB) is measured as the ratio between the peak value after the signal transition to the settled value of the voltage in one bit period. 0 = 0 dB 1 = –1 dB 3 = –2 dB 7 = –4.1 dB 15 = –6.2 dB 31 = –8.2 dB 63 = –11.5 dB
1-0	0	W-0h	0h	Must write 0

8.5.3.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h)

Figure 127. Register 16h

7	6	5	4	3	2	1	0
0	0	0	0	0	0	JESD PLL MODE
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 62. Register 16h Field Descriptions

Bit	Field	Type	Reset	Description
7-2	0	W	0h	Must write 0
1-0	JESD PLL MODE	R/W	0h	These bits select the JESD PLL multiplication factor and must match the JESD MODE setting. 00 = 20X mode 01 = Not used 10 = 40X mode 11 = Not used Refer to Table 13 for Programming Summary of DDC modes and JESD Link Configuration.

8.5.3.6.3 Register 17h (address = 17h), JESD Analog Page (6A00h)

Figure 128. Register 17h

7	6	5	4	3	2	1	0
0	PLL RESET	0	0	0	0	0	0
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 63. Register 17h Field Descriptions

Bit	Field	Type	Reset	Description
7	0	W	0h	Must write 0
6	PLL RESET	R/W	0h	Pulse this bit after powering up the device; see Table 66. 0 = Default 0 → 1 → 0 = The PLL RESET bit is pulsed.
5-0	0	W	0h	Must write 0

8.5.3.6.4 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)

Figure 129. Register 1Ah

7	6	5	4	3	2	1	0
0	0	0	0	0	0	FOVR CHA	0
W-0h	W-0h	W-0h	W-0h	W-0h	W-0h	R/W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 64. Register 1Ah Field Descriptions

Bit	Field	Type	Reset	Description
7-2	0	W	0h	Must write 0
1	FOVR CHA	R/W	0h	This bit outputs the FOVR signal for channel A on the PDN pin. FOVR CHA EN (register 1Bh, bit 3) must be enabled for this bit to function. 0 = Normal operation 1 = The FOVR signal of channel A is available on the PDN pin
0	0	W	0h	Must write 0

8.5.3.6.5 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)

Figure 130. Register 1Bh

7	6	5	4	3	2	1	0
JESD SWING			0	FOVR CHA EN	0	0	0
R/W-0h			W-0h	R/W-0h	W-0h	W-0h	W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 65. Register 1Bh Field Descriptions

Bit	Field	Type	Reset	Description
7-5	JESD SWING	R/W	0h	These bits select the output amplitude V_OD (mV_PP) of the JESD transmitter (for all lanes). 0 = 860 mV_PP 1 = 810 mV_PP 2 = 770 mV_PP 3 = 745 mV_PP 4 = 960 mV_PP 5 = 930 mV_PP 6 = 905 mV_PP 7 = 880 mV_PP
4	0	W	0h	Must write 0
3	FOVR CHA EN	R/W	0h	This bit enables overwrites of the PDN pin with the FOVR signal from channel A. 0 = Normal operation 1 = PDN is overwritten
2-0	0	W	0h	Must write 0

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8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Analog Inputs

8.3.2 DDC Block

8.3.2.1 Decimate-by-2 Filter

Table 1. Corner Frequencies for the Decimate-by-2 Filter

8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer

Table 2. Corner frequencies for the Decimate-by-4 Filter

8.3.2.3 Decimate-by-4 Filter with IQ Outputs

Table 3. Corner Frequencies for a Decimate-by-4 IQ Output Filter

8.3.3 SYSREF Signal

Table 4. LMFSC Clock Frequency

8.3.4 Overrange Indication

8.3.4.1 Fast OVR

8.3.5 Power-Down Mode

Table 5. Register Addresses for Power-Down Modes

Table 6. Power Consumption in Different Power-Down Settings

8.4 Device Functional Modes

8.4.1 Device Configuration

8.4.1.1 Serial Interface

Table 7. SPI Timing Diagram Legend

Table 8. SPI Timing Requirements

8.4.1.2 Serial Register Write: Analog Bank

8.4.1.3 Serial Register Readout: Analog Bank

8.4.1.4 JESD Bank SPI Page Selection

8.4.1.5 Serial Register Write: JESD Bank

8.4.1.5.1 Individual Channel Programming

8.4.1.6 Serial Register Readout: JESD Bank

8.4.2 JESD204B Interface

8.4.2.1 JESD204B Initial Lane Alignment (ILA)

8.4.2.2 JESD204B Test Patterns

8.4.2.3 JESD204B Frame

8.4.2.4 JESD204B Frame

Table 9. Default Interface Rates

Table 10. Default Frame Assembly

8.4.2.5 JESD204B Frame Assembly with Decimation

Table 11. Interface Rates with Decimation Filter

Table 12. Frame Assembly with Decimation Filter

Table 13. Program Summary of DDC Modes and JESD Link Configuration(1)(2)

8.4.2.5.1 JESD Transmitter Interface

8.4.2.5.2 Eye Diagrams

8.5 Register Maps

8.5.1 Detailed Register Info

Table 14. Register Map

8.5.2 Example Register Writes

Table 15. Global Power Down

Table 16. Two Lanes per Channel Mode (LMFS = 4211)

Table 17. 2X Decimation (LPF for Both Channels) with Four Active Lanes (LMFS = 4222)

8.5.3 Register Descriptions

8.5.3.1 General Registers

8.5.3.1.1 Register 0h (address = 0h)

Table 18. Register 0h Field Descriptions

8.5.3.1.2 Register 3h (address = 3h)

Table 19. Register 3h Field Descriptions

8.5.3.1.3 Register 4h (address = 4h)

Table 20. Register 4h Field Descriptions

8.5.3.1.4 Register 5h (address = 5h)

Table 21. Register 5h Field Descriptions

8.5.3.1.5 Register 11h (address = 11h)

Table 22. Register 11h Field Descriptions

8.5.3.2 Master Page (080h) Registers

8.5.3.2.1 Register 20h (address = 20h), Master Page (080h)

Table 23. Registers 20h Field Descriptions

8.5.3.2.2 Register 21h (address = 21h), Master Page (080h)

Table 24. Register 21h Field Descriptions

8.5.3.2.3 Register 23h (address = 23h), Master Page (080h)

Table 25. Register 23h Field Descriptions

8.5.3.2.4 Register 24h (address = 24h), Master Page (080h)

Table 26. Register 24h Field Descriptions

8.5.3.2.5 Register 26h (address = 26h), Master Page (080h)

Table 27. Register 26h Field Descriptions

8.5.3.2.6 Register 39h (address = 39h), Master Page (080h)

Table 28. Register 39h Field Descriptions

8.5.3.2.7 Register 3Ah (address = 3Ah), Master Page (080h)

Table 13. Program Summary of DDC Modes and JESD Link Configuration⁽¹⁾⁽²⁾