8.3.1 Analog Inputs

The ADS54J60 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source, which enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to VCM using 600-Ω resistors, allowing for ac-coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.475 V) and (VCM – 0.475 V), resulting in a 1.9-V_PP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 1.2 GHz. An equivalent analog input network diagram is shown in Figure 58.

Figure 58. Analog Input Network

The input bandwidth shown in Figure 59 is measured with respect to a 50-Ω differential input termination at the ADC input pins. Figure 60 shows the signal processing done inside the DDC block of the ADS54J60.

Figure 59. Transfer Function versus Frequency

1. In IQ decimate-by-4 mode, the mixer frequency is fixed at f_mix = f_S / 4. For f_S = 1 GSPS and f_mix = 250 MHz.

Figure 60. DDC Block