ZHCSE42D April 2015 – April 2019 ADS54J60
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | SUBCLASS | 0 | 0 | 0 |
W-0h | W-0h | W-0h | W-0h | R/W-1h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | W | 0h | Must write 0 |
3 | SUBCLASS | R/W | 1h | This bit sets the JESD204B subclass.
000 = Subclass 0 backward compatible with JESD204A 001 = Subclass 1 deterministic latency using the SYSREF signal |
2-0 | 0 | W | 0h | Must write 0 |