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ZHCSGX5 October 2017 ADS54J64

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RMP|72
- MPQF396A

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	AVDD19	–0.3	2.1	V
	AVDD	–0.3	1.4
	DVDD	–0.3	1.4
Voltage between AGND and DGND		–0.3	0.3	V
Voltage applied to input pins	INAP, INBP, INAM, INBM, INCP, INDP, INCM, INDM	–0.3	2.1	V
	CLKINP, CLKINM	–0.3	AVDD + 0.3
	SYSREFP, SYSREFM	–0.3	1.9
	SCLK, SEN, SDIN, RESET, SYNCbABP, SYNCbABM, SYNCbCDP, SYNCbCDM, PDN, TRIGAB, TRIGCD	–0.2	AVDD19 + 0.3
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
Supply voltage range	AVDD19		1.8	1.9	2	V
	AVDD		1.1	1.15	1.2
	DVDD		1.1	1.15	1.2
Analog inputs	Differential input voltage range			1.1		V_PP
Analog inputs	Input common-mode voltage (VCM)		1.3			V
Clock inputs	Input clock frequency, device clock frequency		400		1000	MHz
	Input clock amplitude differential (V_CLKP – V_CLKM)	Sine wave, ac-coupled		1.5		V_PP
		LVPECL, ac-coupled		1.6
		LVDS, ac-coupled		0.7
	Input device clock duty cycle, default after reset		45%	50%	55%
Temperature	Operating free-air, T_A		–40		100⁽²⁾	ºC
	Operating junction, T_J				105⁽¹⁾
	Specified maximum, measured at the device footprint thermal pad on the printed circuit board, T_P-MAX				104.5⁽¹⁾

(1) Prolonged use above this junction temperature can increase the device failure-in-time (FIT) rate.

(1) The recommended maximum temperature at the PCB footprint thermal pad assumes the junction-to-package bottom thermal resistance, R_θJC(bot) = 0.2°C/W, the thermal resistance of the device thermal pad connection to the PCB footprint is negligible, and the device power consumption is 2.5 W.

(2) Assumes system thermal design meets the T_J specification.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS54J64	UNIT
		RMP (VQFNP)
		72 PINS
R_θJA	Junction-to-ambient thermal resistance ⁽¹⁾	22.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance ⁽²⁾	5.1	°C/W
R_θJB	Junction-to-board thermal resistance ⁽²⁾	2.4	°C/W
ψ_JT	Junction-to-top characterization parameter ⁽³⁾	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter ⁽⁴⁾	2.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance ⁽⁵⁾	0.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

6.5 Electrical Characteristics

typical values are at T_A = 25°C, full temperature range is from T_MIN = –40°C to T_MAX = +100°C, input clock frequency = 1 GHz, 50% clock duty cycle, output sample rate = 500 MSPS, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and f_IN = 190 MHz (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
GENERAL
	ADC sampling rate				1	GSPS
	Resolution		14			Bits
POWER SUPPLY
AVDD19	1.9-V analog supply		1.85	1.9	1.95	V
AVDD	1.15-V analog supply		1.1	1.15	1.2	V
DVDD	1.15-V digital supply		1.1	1.15	1.2	V
I_AVDD19	1.9-V analog supply current	100-MHz, full-scale input on all four channels		618		mA
I_AVDD	1.15-V analog supply current	100-MHz, full-scale input on all four channels		415		mA
I_DVDD	1.15-V digital supply current	DDC bypass mode (mode 8), 100-MHz, full-scale input on all four channels		629		mA
		Mode 3, 100-MHz, full-scale input on all four channels		730
		Mode 0 and 2, 100-MHz, full-scale input on all four channels		674
		Mode 1, 4, 6, and 7, 100-MHz, full-scale input on all four channels		703
P_DIS	Total power dissipation	DDC bypass mode (mode 8), 100-MHz, full-scale input on all four channels		2.37		W
		Mode 3, 100-MHz, full-scale input on all four channels		2.49
		Mode 0 and 2, 100-MHz, full-scale input on all four channels		2.42
		Mode 1, 4, 6, and 7, 100-MHz, full-scale input on all four channels		2.46
	Global power-down power dissipation	Full-scale input on all four channels		120		mW
ANALOG INPUTS
	Differential input full-scale voltage			1.1		V_PP
	Input common-mode voltage			1.3		V
	Differential input resistance	At f_IN = dc		4		kΩ
	Differential input capacitance			2.5		pF
	Analog input bandwidth (3 dB)			1000		MHz
ISOLATION
	Crosstalk⁽¹⁾ isolation between near channels (channels A and B are near to each other, channels C and D are near to each other)	f_IN = 10 MHz		75		dBFS
		f_IN = 100 MHz		75
		f_IN = 170 MHz		74
		f_IN = 270 MHz		72
		f_IN = 370 MHz		71
		f_IN = 470 MHz		70
	Crosstalk⁽¹⁾ isolation between far channels (channels A and B are far from channels C and D)	f_IN = 10 MHz		110		dBFS
		f_IN = 100 MHz		110
		f_IN = 170 MHz		110
		f_IN = 270 MHz		110
		f_IN = 370 MHz		110
		f_IN = 470 MHz		110
CLOCK INPUT
	Internal clock biasing	CLKINP and CLKINM pins are connected to the internal biasing voltage through a 5-kΩ resistor		0.7		V

(1) Crosstalk is measured with a –1-dBFS input signal on the aggressor channel and no input on the victim channel.

6.6 AC Performance

PARAMETER		TEST CONDITIONS	MIN	TYP	MIN	TYP	UNIT
PARAMETER		TEST CONDITIONS	DDC BYPASS MODE		DECIMATE-BY-4 (DDC Mode 2)		UNIT
SNR	Signal-to-noise ratio	f_IN = 10 MHz, A_IN = –1 dBFS		69.9		72.2	dBFS
		f_IN = 70 MHz, A_IN = –1 dBFS		69.6		71.8
		f_IN = 190 MHz, A_IN = –1 dBFS		69.2		71.8
		f_IN = 190 MHz, A_IN = –3 dBFS	66.5	69.6		71
		f_IN = 300 MHz, A_IN = –3 dBFS		69.3		71.7
		f_IN = 370 MHz, A_IN = –3 dBFS		68.7		71.3
		f_IN = 470 MHz, A_IN = –3 dBFS		68.4		69.8
NSD	Noise spectral density	f_IN = 10 MHz, A_IN = –1 dBFS		–153.9		–153.2	dBFS/Hz
		f_IN = 70 MHz, A_IN = –1 dBFS		–153.6		–152.8
		f_IN = 190 MHz, A_IN = –1 dBFS		–153.2		–152.7
		f_IN = 190 MHz, A_IN = –3 dBFS	–150.5	–153.6		–153.2
		f_IN = 300 MHz, A_IN = –3 dBFS		–152.8		–152.7
		f_IN = 370 MHz, A_IN = –3 dBFS		–152.5		–152.2
		f_IN = 470 MHz, A_IN = –3 dBFS		–151.5		–151
SFDR⁽¹⁾	Spurious-free dynamic range	f_IN = 10 MHz, A_IN = –1 dBFS		83		83	dBc
		f_IN = 70 MHz, A_IN = –1 dBFS		81		100
		f_IN = 190 MHz, A_IN = –1 dBFS		87		100
		f_IN = 190 MHz, A_IN = –3 dBFS	78	88		98
		f_IN = 300 MHz, A_IN = –3 dBFS		79		98
		f_IN = 370 MHz, A_IN = –3 dBFS, input clock frequency = 983.04 MHz		82		70
		f_IN = 470 MHz, A_IN = –3 dBFS		78		76
SINAD	Signal-to-noise and distortion ratio	f_IN = 10 MHz, A_IN = –1 dBFS		68.5		70.6	dBFS
		f_IN = 70 MHz, A_IN = –1 dBFS		68.5		70.6
		f_IN = 190 MHz, A_IN = –1 dBFS		68.2		72.2
		f_IN = 190 MHz, A_IN = –3 dBFS		68.5		73
		f_IN = 300 MHz, A_IN = –3 dBFS		68.9		72.3
		f_IN = 370 MHz, A_IN = –3 dBFS		68		68.2
		f_IN = 470 MHz, A_IN = –3 dBFS		68		69
HD2⁽¹⁾	Second-order harmonic distortion	f_IN = 10 MHz, A_IN = –1 dBFS		–83		–90	dBc
		f_IN = 70 MHz, A_IN = –1 dBFS		–82		–100
		f_IN = 190 MHz, A_IN = –1 dBFS		–85		–98
		f_IN = 190 MHz, A_IN = –3 dBFS	–78	–86		–100
		f_IN = 300 MHz, A_IN = –3 dBFS		–82		–100
		f_IN = 370 MHz, A_IN = –3 dBFS input clock frequency = 983.04 MHz		–82		–69
		f_IN = 470 MHz, A_IN = –3 dBFS		–100		–94
HD3⁽¹⁾	Third-order harmonic distortion	f_IN = 10 MHz, A_IN = –1 dBFS		–83		–85	dBc
		f_IN = 70 MHz, A_IN = –1 dBFS		–81		–100
		f_IN = 190 MHz, A_IN = –1 dBFS		–92		–100
		f_IN = 190 MHz, A_IN = –3 dBFS	–78	–92		–100
		f_IN = 300 MHz, A_IN = –3 dBFS		–90		–100
		f_IN = 370 MHz, A_IN = –3 dBFS		–90		–100
		f_IN = 470 MHz, A_IN = –3 dBFS		–80		–79
Non HD2, HD3	Spurious-free dynamic range (excluding HD2, HD3)	f_IN = 10 MHz, A_IN = –1 dBFS		95		–100	dBFS
		f_IN = 70 MHz, A_IN = –1 dBFS		95		–92
		f_IN = 190 MHz, A_IN = –1 dBFS		95		–100
		f_IN = 190 MHz, A_IN = –3 dBFS	87	95		–98
		f_IN = 300 MHz, A_IN = –3 dBFS		95		–100
		f_IN = 370 MHz, A_IN = –3 dBFS		95		–100
		f_IN = 470 MHz, A_IN = –3 dBFS		93		–100
THD⁽¹⁾	Total harmonic distortion	f_IN = 10 MHz, A_IN = –1 dBFS		–81		–83	dBc
		f_IN = 70 MHz, A_IN = –1 dBFS		–79		–100
		f_IN = 190 MHz, A_IN = –1 dBFS		–83		–100
		f_IN = 190 MHz, A_IN = –3 dBFS		–85		–100
		f_IN = 300 MHz, A_IN = –3 dBFS		–81		–100
		f_IN = 370 MHz, A_IN = –3 dBFS		–76		–68
		f_IN = 470 MHz, A_IN = –3 dBFS		–82		–80
IMD3	Two-tone, third-order intermodulation distortion	f₁ = 185 MHz, f₂ = 190 MHz, A_IN = –10 dBFS		–90		–87	dBFS
		f₁ = 365 MHz, f₂ = 370 MHz, A_IN = –10 dBFS		–90		–94
		f₁ = 465 MHz, f₂ = 470 MHz, A_IN = –10 dBFS		–85		–85

(1) Harmonic distortion performance can be significantly improved by using the frequency planning explained in the Frequency Planning section.

6.7 Digital Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, TRIGAB, TRIGCD)⁽¹⁾
V_IH	High-level input voltage	All digital inputs support 1.2-V and 1.8-V logic levels	0.8			V
V_IL	Low-level input voltage	All digital inputs support 1.2-V and 1.8-V logic levels			0.4	V
I_IH	High-level input current	SEN		0		µA
I_IH	High-level input current	RESET, SCLK, SDIN, PDN, TRIGAB, TRIGCD		50		µA
I_IL	Low-level input current	SEN		50		µA
I_IL	Low-level input current	RESET, SCLK, SDIN, PDN, TRIGAB, TRIGCD		0		µA
	Input capacitance			4		pF
DIGITAL INPUTS
V_D	Differential input voltage	SYSREFP, SYSREFM	0.35	0.45	0.55	V
V_D	Differential input voltage	SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP	0.35	0.45	0.8	V
V_{(CM_DIG)}	Common-mode voltage for SYSREF	SYSREFP, SYSREFM	0.9	1.2	1.4	V
V_{(CM_DIG)}	Common-mode voltage for SYSREF	SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP	0.9	1.2	1.4	V
DIGITAL OUTPUTS (SDOUT, TRDYAB, TRDYCD)
V_OH	High-level output voltage	100-µA current	AVDD19 – 0.2			V
V_OL	Low-level output voltage	100-µA current			0.2	V
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)⁽²⁾
V_OD	Output differential voltage	With default swing setting		700		mV_PP
V_OC	Output common-mode voltage		450			mV
	Transmitter short-circuit current	Transmitter pins shorted to any voltage between –0.25 V and 1.45 V	–100		100	mA
z_os	Single-ended output impedance			50		Ω
	Output capacitance	Output capacitance inside the device, from either output to ground		2		pF

(1) The RESET, SCLK, SDIN, and PDN pins have a 10-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 10-kΩ (typical) pullup resistor to DVDD.

(2) 50-Ω, single-ended external termination to DVDD.

6.8 Timing Characteristics

			MIN	TYP	MAX	UNITS
SAMPLE TIMING CHARACTERISTICS
	Aperture delay		0.55		0.92	ns
	Aperture delay matching between two channels on the same device			±100		ps
	Aperture delay matching between two devices at the same temperature and supply voltage			±100		ps
	Aperture jitter			100		f_S rms
	Wake-up time	Global power-down		10		ms
	Wake-up time	Pin power-down (fast power-down)		5		µs
	Data latency: ADC sample to digital output	DDC bypass mode		116		Input clock cycles
	Data latency: ADC sample to digital output	DDC mode 0		204		Input clock cycles
t_{SU_SYSREF}	Setup time for SYSREF, referenced to input clock rising edge		350		900	ps
t_{H_SYSREF}	Hold time for SYSREF, referenced to input clock rising edge		100			ps
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
	Unit interval		100			ps
	Serial output data rate				10	Gbps
	Total jitter for BER of 1E-15 and lane rate = 10 Gbps			24		ps
	Random jitter for BER of 1E-15 and lane rate = 10 Gbps			0.95		ps rms
	Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps			8.8		ps, pk-pk
t_R, t_F	Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps			35		ps

Figure 1. Latency Timing Diagram in DDC Bypass Mode

6.9 Typical Characteristics: DDC Bypass Mode

typical values are at T_A = 25°C, full temperature range is from T_MIN = –40°C to T_MAX = +100°C, device sampling frequency = 1 GSPS, 50% clock duty cycle, output sample rate = 500 MSPS, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and f_IN = 190 MHz (unless otherwise noted)

f_IN = 100 MHz, A_IN = –1 dBFS, SNR = 69.57 dBFS,
SFDR = 85.23 dBc, SFDR = 102.09 dBc (non 23)

Figure 2. FFT for 100-MHz Input Signal

f_IN = 190 MHz, A_IN = –3 dBFS, SNR = 69.60 dBFS,
SFDR = 88.45 dBc, SFDR = 99.78 dBc (non 23)

Figure 4. FFT for 190-MHz Input Signal

f_IN = 190 MHz, A_IN = –20 dBFS, SNR = 70.23 dBFS,
SFDR = 81.71 dBc, SFDR = 81.71 dBc (non 23)

Figure 6. FFT for 190-MHz Input Signal

f_IN = 270 MHz, A_IN = –3 dBFS, SNR = 69.27 dBFS,
SFDR = 82.98 dBc, SFDR = 95.4 dBc (non 23)

Figure 8. FFT for 270-MHz Input Signal

f_IN = 470 MHz, A_IN = –3 dBFS, SNR = 68.21 dBFS,
SFDR = 79.85 dBc, SFDR = 99.12 dBc (non 23)

Figure 10. FFT for 470-MHz Input Signal

f_IN1 = 160 MHz, f_IN2 = 170 MHz, IMD = 103.44 dBFS,
each tone at –10 dBFS

Figure 12. FFT for Two-Tone Input Signal

f_IN1 = 340 MHz, f_IN2 = 350 MHz, IMD = 95.08 dBFS,
each tone at –10 dBFS

Figure 14. FFT for Two-Tone Input Signal

Figure 16. HD3 vs Input Frequency

Figure 18. SNR vs Input Frequency and Temperature

Figure 20. HD2 vs Input Frequency and Temperature

Figure 22. HD3 vs Input Frequency and AVDD19 Supply

Figure 24. HD3 vs Input Frequency and AVDD Supply

Figure 26. HD3 vs Input Frequency and DVDD Supply

f_IN = 370 MHz

Figure 28. Performance vs Input Signal Amplitude

f_IN1 = 340 MHz, f_IN2 = 350 MHz

Figure 30. IMD vs Input Amplitude

f_IN = 190 MHz, A_IN = –1 dBFS, f_Noise = 5 MHz, A_Noise = 50 mV_PP

Figure 32. PSRR vs Power-Supply Noise Frequency

f_IN = 190 MHz, A_IN = –1 dBFS, f_Noise = 5 MHz, A_Noise = 50 mV_PP

Figure 34. CMRR vs Common-Mode Noise Frequency

f_IN = 190 MHz, A_IN = –1 dBFS, SNR = 69.23 dBFS,
SFDR = 86.83 dBc, SFDR = 91.23 dBc (non 23)

Figure 3. FFT for 190-MHz Input Signal

f_IN = 190 MHz, A_IN = –10 dBFS, SNR = 70.05 dBFS,
SFDR = 93.27 dBc, SFDR = 97.26 dBc (non 23)

Figure 5. FFT for 190-MHz Input Signal

f_IN = 230 MHz, A_IN = –1 dBFS, SNR = 69.17 dBFS,
SFDR = 85.29 dBc, SFDR = 89.30 dBc (non 23)

Figure 7. FFT for 230-MHz Input Signal

f_IN = 370 MHz, A_IN = –3 dBFS, SNR = 68.36 dBFS,
SFDR = 81.37 dBc, SFDR = 97.28 dBc (non 23)

Figure 9. FFT for 370-MHz Input Signal

f_IN1 = 160 MHz, f_IN2 = 170 MHz, IMD = 102.68 dBFS,
each tone at –7 dBFS

Figure 11. FFT for Two-Tone Input Signal

f_IN1 = 340 MHz, f_IN2 = 350 MHz, IMD = 84.34 dBFS,
each tone at –7 dBFS

Figure 13. FFT for Two-Tone Input Signal

Figure 15. SNR vs Input Frequency

Figure 17. HD2 vs Input Frequency

Figure 19. HD3 vs Input Frequency and Temperature

Figure 21. SNR vs Input Frequency and AVDD19 Supply

Figure 23. SNR vs Input Frequency and AVDD Supply

Figure 25. SNR vs Input Frequency and DVDD Supply

f_IN = 190 MHz

Figure 27. Performance vs Input Signal Amplitude

f_IN1 = 160 MHz, f_IN2 = 170 MHz

Figure 29. IMD vs Input Amplitude

f_IN = 190 MHz, A_IN = –1 dBFS, f_Noise = 5 MHz,
A_Noise = 50 mV_PP, SFDR = 73.5 dBFS

Figure 31. Power-Supply Rejection Ratio FFT
for 50-mV Noise on AVDD Supply

f_IN = 190 MHz, A_IN = –1 dBFS, f_Noise = 5 MHz,
A_Noise = 50 mV_PP, SFDR = 63.12 dBFS

Figure 33. Common-Mode Rejection Ratio FFT

Figure 35. Power Consumption vs Sampling Speed

6.10 Typical Characteristics: Mode 2

typical values are at T_A = 25°C, full temperature range is from T_MIN = –40°C to T_MAX = +100°C, device sampling frequency = 1 GSPS, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –1-dBFS differential input, and f_IN = 190 MHz (unless otherwise noted)

f_IN = 150 MHz, A_IN= –1 dBFS, SNR = 72.85 dBFS,
SFDR = 84.41 dBc, SFDR = 100.99 dBc (non 23)

Figure 36. FFT for 150-MHz Input Signal

f_IN = 300 MHz, A_IN= –3 dBFS, SNR = 72.3 dBFS,
SFDR = 100.31 dBc, SFDR = 100.75 dBc (non 23)

Figure 38. FFT for 300-MHz Input Signal

f_IN = 190 MHz, A_IN= –1 dBFS, SNR = 72.37 dBFS,
SFDR = 99.95 dBc, SFDR = 100.76 dBc (non 23)

Figure 37. FFT for 190-MHz Input Signal

f_IN = 350 MHz, A_IN= –3 dBFS, SNR = 72.02 dBFS,
SFDR = 79.23 dBc, SFDR = 96.42 dBc (non 23)

Figure 39. FFT for 350-MHz Input Signal

6.11 Typical Characteristics: Mode 0

f_IN = 100 MHz, A_IN= –1 dBFS, SNR = 70.16 dBFS,
SFDR = 84.95 dBc, SFDR = 95.41 dBc (non 23)

Figure 40. FFT for 100-MHz Input Signal

f_IN = 220 MHz, A_IN= –1 dBFS, SNR = 69.27 dBFS,
SFDR = 87.66 dBc, SFDR = 91.04 dBc (non 23)

Figure 42. FFT for 220-MHz Input Signal

f_IN = 170 MHz, A_IN= –1 dBFS, SNR = 69.35 dBFS,
SFDR = 86.46 dBc, SFDR = 89.27 dBc (non 23)

Figure 41. FFT for 170-MHz Input Signal

6.12 Typical Characteristics: Dual ADC Mode

f_IN = 230 MHz, A_IN= –1 dBFS, SNR = 68.11 dBFS,
SFDR = 77.01 dBc, interleaving spur = –42.85 dBFS

Figure 43. FFT for 230-MHz Input Signal

Figure 45. Interleaving Spur vs Input Frequency

f_IN = 470 MHz, A_IN= –1 dBFS, SNR = 66.56 dBFS,
SFDR = 72.32 dBc, interleaving spur = –36.96 dBFS

Figure 44. FFT for 470-MHz Input Signal