Table 1. ADS54J64 Operating Modes

7.4.1.1 Numerically Controlled Oscillators (NCOs) and Mixers

The ADS54J64 is equipped with a complex numerically-controlled oscillator. The oscillator generates a complex exponential sequence: x[n] = e^jωn. The frequency (ω) is specified by the 16-bit register setting. The complex exponential sequence is multiplied by the real input from the ADC to mix the desired carrier down to 0 Hz.

The NCO frequency setting is set by the 16-bit register value, NCO_FREQ[n]:

Equation 1.

7.4.1.2 Decimation Filter

The ADS54J64 has two decimation filters (decimate-by-2) in the data path. The first stage of the decimation filter is non-programmable and is used in all functional modes. The second stage of decimation, available in DDC mode 2 and 6, can be used to obtain noise and linearity improvement for low bandwidth applications.

7.4.1.2.1 Stage-1 Filter

The first-stage filter is used for decimation of the 2x interleaved data from f_CLK to f_CLK / 2. Figure 50 and Figure 51 show the frequency response and pass-band ripple of the first-stage decimation filter, respectively.

Input clock rate = 1 GHz

Figure 50. Decimation Filter Response vs Frequency

Input clock rate = 1 GHz

Figure 51. Decimation Filter Pass-Band Ripple vs Frequency

7.4.1.2.2 Stage-2 Filter

The second-stage filter is used for decimating the data from a sample rate of f_CLK / 2 to f_CLK / 4. Figure 52 and Figure 53 show the frequency response and pass-band ripple of the second-stage filter, respectively.

Input clock rate (fCLK) = 1 GHz

Figure 52. Decimation Filter Response vs Frequency

Input clock rate (fCLK) = 1 GHz

Figure 53. Decimation Filter Pass-Band Ripple vs Frequency

7.4.1.3 Mode 0: Decimate-by-4 With IQ Outputs and f_S / 4 Mixer

In mode 0, the DDC block includes a fixed frequency ±f_S / 4 complex digital mixer preceding the second-stage decimation filters. Figure 54 shows that the IQ pass band is approximately ±100 MHz centered at f_S / 8 or 3f_S / 8.

Figure 54. Operating Mode 0

7.4.1.4 Mode 1: Decimate-by-4 With IQ Outputs and 16-Bit NCO

In mode 1, the DDC block includes a 16-bit frequency resolution complex digital mixer, as shown in Figure 55, preceding the second-stage decimation filters.

Figure 55. Operating Mode 1

7.4.1.5 Mode 2: Decimate-by-4 With Real Output

In mode 2, the DDC block cascades two decimate-by-2 filters. Each filter can be configured as low pass (LP) or high pass (HP), as shown in Table 2, to allow down conversion of different frequency ranges. Figure 56 shows that the LP, HP and HP, LP output spectra are inverted.

Figure 56. Operating in Mode 2

7.4.1.6 Mode 3: Decimate-by-2 Real Output With Frequency Shift

In mode 3, the DDC block includes a 16-bit complex NCO digital mixer followed by a f_S / 4 mixer with a real output to center the band at f_S / 4. As shown in Figure 57, the NCO must be set to a value different from ±f_S / 4, or else the samples are zeroed.

Figure 57. Operating Mode 3

7.4.1.7 Mode 4: Decimate-by-4 With Real Output

In mode 4, the DDC block includes a 16-bit complex NCO digital mixer preceding the second-stage decimation filter. As shown in Figure 58, the signal is then mixed with f_OUT / 4 to generate a real output. The bandwidth available in this mode is 100 MHz.

Figure 58. Operating Mode 4

7.4.1.8 Mode 6: Decimate-by-4 With IQ Outputs for Up to 110 MHz of IQ Bandwidth

In mode 6, the DDC block shown in Figure 59 includes a 16-bit complex NCO digital mixer preceding a second-stage filter with a decimate-by-4 complex, generating a complex output at f_S / 8.

Figure 59. Operating Mode 6

7.4.1.9 Mode 7: Decimate-by-4 With Real Output and Zero Stuffing

In mode 7, the DDC block includes a 16-bit complex NCO digital mixer preceding the second-stage decimation filter. The signal is then mixed with f_OUT / 4, as shown in Figure 60, to generate a real output that is then doubled in sample rate by zero-stuffing every other sample. The bandwidth available in this mode is 100 MHz.

Figure 60. Operating Mode 7

7.4.1.10 Mode 8: DDC Bypass Mode

In mode 8, the DDC block is bypassed as shown in Figure 61 and the 2x decimated data are available on the JESD output. The decimation filter can be configured to be high pass or low pass using an SPI register bit. The stop-band attenuation is approximately 40 dB and the available bandwidth is 225 MHz. The decimation filter response is illustrated in Figure 50 and Figure 51.

Figure 61. Operating Mode 8

7.4.1.11 Averaging Mode

In dual ADC mode, two channels (channels A, B and C, D) are averaged and given out as a single output. As a result, the device operates in a dual-channel mode with 2x interleaved sample rate. For a 1-GSPS input clock, the averaged output at 1 GSPS is available on two JESD lanes, each operating at 10 Gbps. Figure 62 shows the device supporting an averaging of channels A and B. An identical averaging path is available for channels C and D. Configure the device in mode 8 before enabling dual ADC mode through SPI register writes.

Figure 62. Averaging Mode for Channels A and B (C and D Averaging is Identical)

7.4.1.12 Overrange Indication

The ADS54J64 provides a fast overrange indication that can be presented in the digital output data stream via SPI configuration. When the FOVR indication is embedded in the output data stream as shown in Figure 63, this indication replaces the LSB (D0) of the 16 bits going to the 8b, 10b encode.

Figure 63. FOVR Timing Diagram

The fast overrange feature of the ADS54J64 is configured using an upper (FOVR Hi) and a lower (FOVR Lo) 8-bit threshold that are compared against the partial ADC output of the initial pipeline stages. Figure 64 shows the FOVR high and FOVR low thresholds.

The two thresholds are configured via the SPI register where a setting of 136 maps to the maximum ADC code for a high FOVR, and a setting of 8 maps to the minimum ADC code for a low FOVR.

Figure 64. FOVR High and FOVR Low Thresholds

Equation 2 calculates the FOVR threshold from a full-scale input based on the ADC code:

Equation 2.

Therefore, a threshold of –0.5 dBFS from full-scale can be set with:

• FOVR high = 132 (27h, 84h)
• FOVR low = 12 (28h, 0Ch)

Table 3. Available JESD204B Formats and Valid Ranges for the ADS54J64

Table 4. Detailed Frame Assembly for Four-Lane Modes (Modes 0, 1, 3, 6, 7, and 8)

Table 5. Detailed Frame Assembly for Two-Lane Modes (Modes 2 and 4)

Table 6. Detailed Frame Assembly for Four-Lane Mode (2x Interleaved Dual ADC)

7.5.4.1 SerDes Transmitter Interface

As shown in Figure 69, each 10-Gbps SerDes transmitter output requires ac-coupling between the transmitter and receiver. Terminate the differential pair with 100 Ω as close to the receiving device as possible to avoid unwanted reflections and signal degradation.

Figure 69. SerDes Transmitter Connection to Receiver

7.5.4.2 SYNCb Interface

The ADS54J64 supports single SYNCb control (where the SYNCb input controls all four JESD204B links) or dual SYNCb control (where one SYNCb input controls two JESD204B lanes: DA, DB and DC, DD). When using the single SYNCb control, connect the unused input to a differential logic high (SYNCbxxP = DVDD, SYNCbxxM = 0 V).

7.5.4.3 Eye Diagram

Figure 70 to Figure 73 show the serial output eye diagrams of the ADS54J64 at 7.5 Gbps and 10 Gbps with default and increased output voltage swing against the JESD204B mask.

Figure 70. Eye at 10-Gbps Bit Rate With
Default Output Swing

Figure 72. Eye at 10-Gbps Bit Rate With
Increased Output Swing

Figure 71. Eye at 7.5-Gbps Bit Rate With
Default Output Swing

Figure 73. Eye at 7.5-Gbps Bit Rate With
Increased Output Swing

7.5.5.1 Details of the Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), SDIN (serial data input data), and SDOUT (serial data output) pins. Serially shifting bits into the device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active (low). Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The first 16 bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequencies from 10 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

7.5.5.2 Serial Register Write

The internal registers of the ADS54J64 can be programmed (as shown in Figure 74) by:

1. Driving the SEN pin low
2. Setting the R/W bit = 0
3. Initiating a serial interface cycle specifying the address of the register (A[14:0]) whose content must be written
4. Writing the 8-bit data that is latched in on the SCLK rising edge

The ADS54J64 has several different register pages (page selection in address 11h, 12h). Specify the register page before writing to the desired address. The register page only must be set one time for continuous writes to the same page.

During the write operation, the SDOUT pin is in a high-impedance mode and must float.

Figure 74. Serial Interface Write Timing Diagram

7.5.5.3 Serial Read

Figure 75 shows a typical 4-wire serial register readout. In the default 4-pin configuration, the SDIN pin is the data output from the ADS54J64 during the data transfer cycle when SDOUT is in a high-impedance state. The internal registers of the ADS54J64 can be read out by:

1. Driving the SEN pin low
2. Setting the R/W bit to 1 to enable read back
3. Specifying the address of the register (A[14:0]) whose content must be read back
4. The device outputs the contents (D[7:0]) of the selected register on the SDOUT pin (pin 51)
5. The external controller can latch the contents at the SCLK rising edge

Figure 75. Serial Interface 4-Wire Read Timing Diagram

Table 7. Serial Interface Register Map

7.6.1.1 Register Description

Table 8 lists the access codes for the ADS54J64 registers.