The signal-to-noise ratio of the ADC is limited by three different factors (as shown in Equation 2): the quantization noise is typically not noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input frequencies and the clock jitter sets the SNR for higher input frequencies.

Equation 2.

The SNR limitation resulting from sample clock jitter can be calculated by Equation 3:

Equation 3.

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (120 fs for the ADS54J66) that is set by the noise of the clock input buffer and the external clock jitter. T_Jitter can be calculated by Equation 4:

Equation 4.

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input; a faster clock slew rate also improves the ADC aperture jitter.

The ADS54J66 has a thermal noise of approximately 72 dBFS and an internal aperture jitter of 120 fs.