Apply SYSREF after reset and before configuring the device. After the device is configured to the desired mode, the SYSREF driver can be disabled. Optionally, SYSREF can be masked inside the device using the MASK SYSREF register bit.

The SYSREF signal is sampled by the ADS54J66 device clock, and is used to reset the input clock divider that generates the sampling clock for the two interleaving ADC cores. The SYSREF signal also resets the local multiframe clock (LMFC) counter inside the JESD block, and the divider in the decimation filter block of the data converter. SYSREF is required to be a subharmonic of the LMFC frequency. The LMFC clock frequency depends upon the device clock frequency, the DDC decimation option, and the JESD link settings (LMFS). The SYSREF signal is also recommended to be a low frequency signal (less than 5 MHz) in order to reduce coupling to the signal path both on the PCB as well as internal to the device.

Table 8-3 shows that the external SYSREF signal must be a subharmonic of the internal LMFC clock.

The SYSREF frequency is equal to LMFC / N with N = 0, 1, 2, and so forth.