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ZHCSAM3B December 2012 – April 2022 ADS54T01

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机械数据 (封装 | 引脚)

ZAY|196
- MPBGAL1

散热焊盘机械数据 (封装 | 引脚)

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7.9 Electrical Characteristics

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. AVDD33 = 3.3 V, AVDDC/AVDD18/DVDD/DVDDLVDS/IOVDD = 1.8 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNITS
DIGITAL INPUTS – SRESET, SCLK, SDENB, SDIO, ENABLE
	High-level input voltage	All digital inputs support 1.8-V and 3.3-V logic levels.	0.7 x IOVDD			V
	Low-level input voltage	All digital inputs support 1.8-V and 3.3-V logic levels.			0.3 x IOVDD	V
	High-level input current		–50		200	µA
	Low-level input current		–50		50	µA
	Input capacitance			5		pF
DIGITAL OUTPUTS – SDO
	High-level output voltage	Iload = -100 µA	IOVDD – 0.2			V
	High-level output voltage	Iload = -2 mA	0.8 x IOVDD			V
	Low-level output voltage	Iload = 100 µA			0.2	V
	Low-level output voltage	Iload = 2 mA			0.22 x IOVDD	V
DIGITAL INPUTS – SYNCP/N, TRIGGERP/N
V_ID	Differential input voltage		250	350	450	mV
V_CM	Input common-mode voltage		1.125	1.2	1.375	V
t_SU			500			ps
DIGITAL OUTPUTS – DA[11:0]P/N, DACLKP/N, OVRAP/N, SYNCOUTP/N, TRDYP/N, HRESP/N
V_OD	Output differential voltage	Iout = 3.5 mA	250	350	450	mV
V_OCM	Output common-mode voltage	Iout = 3.5 mA	1.125	1.25	1.375	V
t_su	F_s = 750 Msps	Data valid to zero-crossing of DACLK	320	400		ps
t_h	F_s = 750 Msps	Zero-crossing of DACLK to data becoming invalid	250	320		ps
t_PD	F_s = 750Msps	CLKIN falling edge to DACLK rising edge	3.36	3.69	3.92	ns
t_RISE		10% - 90%	100	150	200	ps
t_FALL		90% - 10%	100	150	200	ps

Figure 7-1 Timing Diagram for 12-Bit DDR Output