ZHCSAM3B December 2012 – April 2022 ADS54T01
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Test Pattern Output
- 8.3.2 Clock Inputs
- 8.3.3 SNR and Clock Jitter
- 8.3.4 Analog Inputs
- 8.3.5 Over-Range Indication
- 8.3.6 Interleaving Correction
- 8.3.7 High-Resolution Output Data
- 8.3.8 Low-Resolution Output Data
- 8.3.9 Full Speed – 7 Bit
- 8.3.10 Decimated Low-Resolution Output Data
- 8.3.11 Multi Device Synchronization
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 9 Power Supply Recommendations
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
8.4.3 Receive Mode: Decimation Filter
Figure 8-14 shows that each channel has a digital filter in the data path.
Figure 8-14 Decimation Filter Block DiagramThe filter can be programmed as a low-pass or a high-pass filter and the normalized frequency response of both filters. The decimation filter response has a 0.1-dB pass-band ripple with approximately 41% pass-band bandwidth. The stop-band attenuation is approximately 40 dB.
Figure 8-15 Decimation Filter Response
Figure 8-16 Decimation Filter Response