The data converter channel consists of two interleaved ADCs each operating at half of the ADC sampling rate but 180° out of phase from each other. The front end track and hold circuitry is operating at the full ADC sampling rate which minimizes the timing mismatch between the two interleaved ADCs. In addition, the ADS54T01 is equipped with internal interleaving correction logic that can be enabled through a SPI register write.

Figure 8-7 Interleaving Correction Block Diagram

The interleaving operation creates 2 distinct and interleaving products:

• Fs/2 – Fin: this spur is created by gain timing mismatch between the ADCs. Since internally the front end track and hold is operated at the full sampling rate, this component is greatly improved and mostly dependent on gain mismatch.
• Fs/2 Spur: due to offset mismatch between ADCs

Figure 8-8 Interleaving Correction Spurs

The auto correction loop can be enabled through a SPI register write in address 0x01. By default, the auto correction function is disabled for lowest possible power consumption. The default settings for the auto correction function should work for most applications. However please contact Texas Instruments if further fine tuning of the algorithm is required.

The auto correction function yields best performance for input frequencies below 250 MHz.