The control of the high-resolution output is shown below along with the two output flags (TRDY and HRES).

Figure 8-17 Triggering High Resolution Mode and Lockout Time

After enabling burst mode, the output data DA[11..0] are forced to low-resolution mode for 2¹³ samples. During that period, any trigger signal is ignored. The completion of the low-resolution sample cycle is signaled by a logic high on the TRDY output pins indicating that a high-resolution (12-bit) data output burst can be triggered by a low-to-high transition on the TRIGGER input. The ADC monitors the TRIGGER input at each rising edge of the input clock.

The high-resolution output data starts with a delay of t_{TRIG_DELAY} = 1-2 DACLK clock cycles and is indicated through the HRES data flag which stays high for all 2^N high-resolution samples. At completion the register value for N is verified and transmission of 2^(N+3) low-resolution data immediately follows. When the last low-resolution sample is output on the output data bus, the flag TRDY is asserted high again indicating the end of the lockout period and the next 2^N high-resolution samples can be triggered again.