ZHCSAM3B December   2012  – April 2022 ADS54T01

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics
    7. 7.7  Electrical Characteristics
    8. 7.8  Electrical Characteristics
    9. 7.9  Electrical Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Test Pattern Output
      2. 8.3.2  Clock Inputs
      3. 8.3.3  SNR and Clock Jitter
      4. 8.3.4  Analog Inputs
      5. 8.3.5  Over-Range Indication
      6. 8.3.6  Interleaving Correction
      7. 8.3.7  High-Resolution Output Data
      8. 8.3.8  Low-Resolution Output Data
      9. 8.3.9  Full Speed – 7 Bit
      10. 8.3.10 Decimated Low-Resolution Output Data
      11. 8.3.11 Multi Device Synchronization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
      2. 8.4.2 Feedback Mode: Burst Mode
      3. 8.4.3 Receive Mode: Decimation Filter
      4. 8.4.4 Manual Trigger Mode
      5. 8.4.5 Auto Trigger Mode
    5. 8.5 Programming
      1. 8.5.1 Device Initialization
      2. 8.5.2 Serial Register Write
      3. 8.5.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
      2. 8.6.2 Description of Serial Interface Registers
  9. 9 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.6.2 Description of Serial Interface Registers

Register AddressRegister Data
A7-A0 in hexD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
03/4 Wire SPIDec
Fil/ Burst		0High/ Low Pass000000Burst rate00Auto Trigger00
D153/4 Wire SPI
Default 0		Enables 4-bit serial interface when set
03-wire SPI is used with SDIO pin operating as bidirectional I/O port
14-wire SPI is used with SDIO pin operating as data input and SDO pin as data output port.
D14DecFil/ Burst
Default 0		2x decimation filter (Receive Mode) is enabled when bit is set
0Burst mode enable
12x decimation filter enabled
D12High/Low Pass
Default 0		(Decimation filter must be enabled first: set bit D14)
0Low Pass
1High Pass
D5Burst Rate
Default 0		Low resolution output data rate in burst mode
0Low resolution (9-bit) full output rate
1Decimated low resolution output (4x decimation, 11-bit resolution)
D2Auto Trigger
Default 0		Enables auto trigger mode in burst mode without the need to control the trigger pin.
0Manual trigger mode using the external trigger input pin
1Auto trigger mode enabled
Register Address Register Data
A7-A0 in hex D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 Corr EN 0 0 0 0 0 0 0 0 0 0 0 Data Format 0 HP Mode1 0
D15Corr EN (should be enabled for maximum performance)
Default 0
0auto gain correction disabled
1auto gain correction enabled
D3Data Format
Default 0
0Two's complement
1Offset Binary
D1HP Mode 1
Default 0
1Must be set to 1 for optimum performance
Register AddressRegister Data
A7-A0 in hexD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
201100Over-range threshold0000000
D14Read back 1.
D13Read back 1.
D10-D7Over-range thresholdThe over-range detection is triggered 12 output clock cycles after the overload condition occurs. The threshold at which the OVR is triggered = 1.0V x [decimal value of <Over-range threshold>]/16. After power up or reset, the default value is 15 (decimal) which corresponds to a OVR threshold of 0.56dB below fullscale (20*log(15/16)). This OVR threshold is applicable to both channels.
Default 1111
Figure 8-22 Over-range Threshold vs. Programmed Value
Register AddressRegister Data
A7-A0 in hexD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
30DC Offset Coff00101100011000
D14DC Offset Corr
Default 1		Starts DC offset correction loop
0Starts offset correction loop
1DC offset correction loop is cleared
D11, 9, 8, 4, 3Must be set to 1 for maximum performance
Default 1
Register Address Register Data
A7-A0 in hex D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
E Sync Select 0 0
D15-D2Sync Select
Default 1010 1010 1010 10		Sync selection for the clock generator block (also need to see address 0x0F)
0000 0000 0000 00Sync is disabled
0101 0101 0101 01Sync is set to one shot (one time synchronization only)
1010 1010 1010 10Sync is derived from SYNC input pins
1111 1111 1111 11not supported
Register Address Register Data
A7-A0 in hex D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
F Sync Select 0 0 0 0 0 VREF Sel 0 0 0 0
D15-D12Sync Select
Default 1010 1010 1010 10		Sync selection for the clock generator block
0000Sync is disabled
0101Sync is set to one shot (one time synchronization only)
1010Sync is derived from SYNC input pins
1111not supported
D6-D4VREF SEL
Default 000		Internal voltage reference selection
0001.0 V
0011.25 V
0100.9 V
0110.8 V
1001.15 V
Othersexternal reference
Register AddressRegister Data
A7-A0 in hexD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
1A0000101100011000
D14, 11, 9, 8, 4, 3Must be set to 1 for maximum performance
Default 1
Register AddressRegister Data
A7-A0 in hexD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
2B0000000Temp Sensor
D8-D0Temp SensorInternal temperature sensor value – read only
Register AddressRegister Data
A7-A0 in hexD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
2CReset
D15-D0Reset
Default 0000		This is a software reset to reset all SPI registers to their default value. Self clears to 0.
1101001011110000Perform software reset
Register Address Register Data
A7-A0 in hex D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
34 0 0 Burst Mode N 0 0 0 0 0 0 0 0 0 0
D13-D10Burst Mode N
Default 0000		This is the parameter that sets the amount of high resolution samples in burst mode
0000N = 10
0001N = 11
......
1111N = 25
Register AddressRegister Data
A7-A0 in hexD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
37Sleep Modes0000000000
D15-D14Sleep Modes
Default 00		Sleep mode selection which is controlled by the ENABLE pin. Sleep modes are active when ENABLE pin goes low.
000000Complete shut downWake up time 2.5 ms
100000Standby modeWake up time 100 µs
110000Deep sleep modeWake up time 20 µs
110101Light sleep modeWake up time 2 µs
Register Address Register Data
A7-A0 in hex D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
38 HP Mode 2 LP Mode TEMP EN FUSE Bias EN SYNC EN TRIG EN 1 1 1 1
D15-D9HP Mode 2
Default 111111111
1Set to 1 for normal operation
D8LP Mode
Default 1		Low power mode
0Set to 0 to turn off unused output buffers
D7TEMP EN
Default 1		Temperature sensor enable
1Set to 1 to enable the temperature sensor
D6FUSE BIAS EN
Default 1		Enables internal bias voltages. Can be disabled after power up for power savings.
0Internal fuse bias powered down
1Internal fuse bias enabled
D5SYNC EN
Default 1		Enables the SYNC input buffer.
0SYNC input buffer disabled
1SYNC input bffer enabled
D4TRIG EN
Default 1		Enables the TRIGGER input buffer.
0TRIGGER input buffer disabled
1TRIGGER input bffer enabled
D3-D0Read back 1
Register AddressRegister Data
A7-A0 in hexD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
3ALVDS Current StrengthLVDS SWInternal LVDS Termination0000DACLK EN00OVRA EN0
D15-D13LVDS Current Strength
Default 000		LVDS output current strength.
0002 mA1003 mA
0012.25 mA1013.25 mA
0102.5 mA1103.5 mA
0112.75 mA1113.75 mA
D12-D11LVDS SW
Default 01		LVDS driver internal switch setting – correct range must be set for setting in D15-D13
012 mA to 2.75 mA
113mA to 3.75mA
D10-D9Internal LVDS Termination
Default 00		Internal termination
002 kΩ
01200 Ω
10200 Ω
11100 Ω
D4DACLK EN
Default 1		Enable DACLK output buffer
0DACLK output buffer powered down
1DACLK output buffer enabled
D1OVRA EN
Default 1		Enable OVRA output buffer
0OVRA output buffer powered down
1OVRA output buffer enabled
Register AddressRegister Data
A7-A0 in hexD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
66LVDS Output Bus EN
D15-D0LVDS Output Bus EN
Default FFFF		Individual LVDS output pin power down
0Output is powered down
1Output is enabled
D15corresponds to TRDYP/N (pins N7, P7)
D14corresponds to HRESP/N (pins N6, P6)
D13SYNCOUTP/N (pins N5, P5)
D12Pins N4, P4 (no connect pins) which are not used and should be powered down for power savings
D11-D0corresponds to DA11-DA0
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |