| THERMAL METRIC(1) |
ADS54T01 |
UNIT |
| ZAY
(NFBGA) |
| 196
PINS |
| θJA |
Junction-to-ambient thermal resistance(2) |
37.6 |
°C/W |
| θJCtop |
Junction-to-case (top) thermal resistance(3) |
6.8 |
°C/W |
| θJB |
Junction-to-board thermal resistance(4) |
16.8 |
°C/W |
| ψJT |
Junction-to-top characterization parameter(5) |
0.2 |
°C/W |
| ψJB |
Junction-to-board characterization parameter(6) |
16.4 |
°C/W |
(2) The junction-to-ambient thermal resistance under natural convection is obtained
in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in
an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold
plate test on the package top. No specific JEDEC-standard test exists, but a
close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an
environment with a ring cold plate fixture to control the PCB temperature, as
described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the
junction temperature of a device in a real system and is extracted from the
simulation data for obtaining RθJA, using a procedure described in
JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the
junction temperature of a device in a real system and is extracted from the
simulation data for obtaining RθJA, using a procedure described in
JESD51-2a (sections 6 and 7).