ZHCSAM3B December 2012 – April 2022 ADS54T01
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Test Pattern Output
- 8.3.2 Clock Inputs
- 8.3.3 SNR and Clock Jitter
- 8.3.4 Analog Inputs
- 8.3.5 Over-Range Indication
- 8.3.6 Interleaving Correction
- 8.3.7 High-Resolution Output Data
- 8.3.8 Low-Resolution Output Data
- 8.3.9 Full Speed – 7 Bit
- 8.3.10 Decimated Low-Resolution Output Data
- 8.3.11 Multi Device Synchronization
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 9 Power Supply Recommendations
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
8.3.2 Clock Inputs
The ADS54T01 clock input can be driven differentially with a sine wave, LVPECL, or LVDS source with little or no difference in performance. The common-mode voltage of the clock input is set to 0.9 V using internal 2-kΩ resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close to the clock inputs as possible to minimize signal reflections and jitter degradation.
Figure 8-3 Recommended Differential Clock Driving Circuit