7.3.2.1 Drive Circuit Recommendations

For optimum performance, the analog inputs must be driven differentially which improves the common-mode noise immunity and even-order harmonic rejection. A resistor in series with each input pin (about 15 Ω) is recommended to damp out ringing caused by package parasitics. Low impedance (< 50 Ω) is required for the common-mode switching currents which can be achieved by using two resistors from each input terminated to the common-mode voltage (VCM).

The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the glitches caused by the opening and closing of the sampling capacitors. The filtering of the glitches can be improved further using an external R-C-R filter.

In addition to the previously listed requirements, the drive circuit may must be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. While doing this, the ADC input impedance must be considered. Figure 46 and Figure 47 show the impedance (Zin = Rin || Cin) looking into the ADC input pins.

Figure 46. ADC Analog Input Resistance (Rin) Across Frequency

Figure 47. ADC Analog Input Capacitance (Cin) Across Frequency

7.3.2.2 Example Driving Circuit

Figure 48 shows an example input configuration using RF transformers. In this example, an external R-C-R filter using a 22-pF capacitor has been used. Together with the series inductor (39 nH), this combination forms a filter and absorbs the sampling glitches. Because of the relatively large capacitor (22 pF) in the R-C-R and the 15-Ω resistors in series with each input pin, this drive circuit has low bandwidth and is suited for low input frequencies.

The drive circuit has been terminated by 50 Ω near the ADC side. The termination is accomplished by a 25-Ω resistor from each input to the 1.5-V common-mode (VCM) from the device. This allows the analog inputs to be biased around the required common-mode voltage.

The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back to back helps minimize this mismatch and good performance is obtained for high frequency input signals. An additional termination resistor pair may be required between the two transformers (enclosed by the dashed lines in Figure 48). The center point of this termination is connected to ground to improve the balance between the P and M sides. The values of the terminations between the transformers and on the secondary side must be chosen to get an effective 50 Ω (in the case of 50-Ω source impedance).

Figure 48. Drive Circuit Using RF Transformers

7.3.2.3 Input Common-Mode

To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1-μF low-inductance capacitor connected to ground. The VCM pin is designed to directly drive the ADC inputs. Each input pin of the ADC sinks a common-mode current in the order of 6uA/MSPS(about 1mA at 80 MSPS) from the external drive circuit.

7.3.2.4 Programmable Fine Gain

ADS556x has programmable fine gain from 0 dB to 6dB in steps of 1 dB. The corresponding full-scale input range varies from 3.6 V_PP down to 2 V_PP. The fine gain is useful, when lower full-scale input ranges are used to get SFDR improvement (See Figure 11 and Figure 27). This is accompanied by corresponding degradation in SNR (see Figure 12 and Figure 28). The gain can be programmed using the register bits GAIN (Table 14).

After reset, the device is initialized to 1 dB fine gain when configured as Serial Interface Mode. The gain of the device in Parallel Mode will depend on the voltage applied on the SCLK pin. See Table 4 for details.

7.4.2.1 Power-Down

The ADS556x device has three power-down modes: global STANDBY, output buffer disabled, and input clock stopped.

7.4.2.2 Power Supply Sequence

During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated inside the device. Externally, the supplies can be driven from separate supplies or from a single supply.

7.4.3.1 DDR LVDS Outputs

In this mode, the 16 data bits and the output clock are put out using LVDS (low voltage differential signal) levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in Figure 54. Therefore, 8 LVDS output pairs are available for the data bits and 1 LVDS output pair for the output clock.

Figure 54. DDR LVDS Outputs

Even data bits (D0, D2 through D14) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3 through D15) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all the data bits (see Figure 55).

Figure 55. DDR LVDS Interface

7.4.3.2 LVDS Buffer Current Programmability

The default LVDS buffer output current is 3.5 mA. Terminating the buffer current by 100 Ω results in logic HIGH of 350 mV and logic LOW of –350 mV. The LVDS buffer currents can also be programmed to 2.5 mA, 4.5 mA, and 1.95 mA using the serial interface. In addition, exists a current double mode exists in which this current is doubled for the data and output clock buffers.

Both the buffer current programming and the current double mode can be done separately for the data buffers and the output clock buffer (<LVDS CURR> register bits).

7.4.3.3 LVDS Buffer Internal Termination

An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially terminated inside the device. These termination resistances are available: 325, 200, and 175 Ω (nominal with ±20% variation). Any combination of these three terminations can be programmed; the effective termination will be the parallel combination of the selected resistances. This results in eight effective terminations from open (no termination) to 75 Ω.

The internal termination helps to absorb any reflections coming from the receiver end, improving the signal integrity. With 100-Ω internal and 100-Ω external termination, the voltage swing at the receiver end is halved (compared to no internal termination). The terminations can be controlled using the <DATA TERM> and <CLKOUT TERM> register bits.

The voltage swing can be restored by using the LVDS current double mode (<CURR DOUBLE> register bit).

7.4.3.4 Parallel CMOS

In this mode, the digital data and output clock are put out as 3.3-V CMOS voltage levels. Each data bit and the output clock is available on a separate pin in parallel. By default, the data outputs are valid during the rising edge of the output clock. The output clock is CLKOUT.

7.4.3.5 Output Clock Position Programmability

In both the LVDS and CMOS modes, the output clock can be moved around the default position which occurs using the SEN pin (as described in Table 6) or using the serial-interface <CLKOUT POSN> register bits (Table 11).

7.4.5.1 Internal Reference

When the device is in internal reference mode, the REFP and REFM voltages are generated internally. The common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog input pins.

7.4.5.2 External Reference

When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the VCM pin is buffered and gained internally, generating the REFP and REFM voltages. The differential input voltage corresponding to full-scale is given by Equation 1. In this mode, the 1.5-V common-mode voltage to bias the input pins must be generated externally.

Table 2. Parallel Pin Definition

7.5.2.1 Using Serial Interface Programming Only

To program using the serial interface, the internal registers must first be reset to the default values, and the RESET pin must be kept low. In this mode, the SEN, SDATA, and SCLK pins function as serial interface pins and are used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET pin (of width greater than 10 ns), or by a high setting on the <RST> bit (D1 in register 0x6C). The Serial Interface section describes the register programming and register reset in more detail.

Because the parallel pins, DFS and MODE, are not used in this mode, they must be tied to ground.

7.5.2.2 Using Both Serial Interface And Parallel Controls

For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE) can also be used to configure the device.

The serial registers must first be reset to the default values and the RESET pin must be kept low. In this mode, the SEN, SDATA, and SCLK pins function as serial interface pins and are used to access the internal registers of ADC. The registers are reset either by applying a pulse on RESET pin or by a high setting on the <RST> bit (D1 in register 0x6C). The Serial Interface section describes the register programming and register reset in more detail.

The parallel interface control pins, DFS and MODE, are used and their function is determined by the appropriate voltage levels as described in Table 7 and Table 8. The voltage levels are derived by using a resistor string as shown in Figure 57. Because some functions are controlled using both the parallel pins and serial registers, the priority between the two is determined by a priority table (Table 3).

Figure 57. Simple Scheme to Configure Parallel Pins

7.5.2.3 Description of Parallel Pins

Table 10. Register 5D

Table 11. Register 62

Table 12. Register 63

Table 13. Register 65

Table 14. Register 68

Table 15. Register 69 and Register 6A

Table 16. Register 6C

Table 17. Register 6D

Table 18. Register 6E

Table 19. Register 7E

Table 20. Register 7F