米6体育平台手机版

ZHCSFY7B January 2017 – December 2021 ADS58J64

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RMP|72
- MPQF396A
RRH|72
- MPQF526

散热焊盘机械数据 (封装 | 引脚)

订购信息

7.4.1.5 Mode 2: Decimate-by-4 With Real Output

In mode 2, the DDC block cascades two decimate-by-2 filters. Each filter can be configured as low pass (LP) or high pass (HP) to allow down conversion of different frequency ranges, as shown in Table 7-2. The LP, HP and HP, LP output spectra are inverted as shown in Figure 7-11.

Figure 7-11 Operating in Mode 2

Table 7-2 ADS58J64 Operating Mode 2 Down-Converted Frequency Ranges

1ST STAGE FILTER	2ND STAGE FILTER	FREQUENCY RANGE WITH CLOCK RATE OF 983.04 MHz	BANDWIDTH WITH CLOCK RATE OF 983.04 MHz	FREQUENCY RANGE WITH CLOCK RATE OF 737.28 MHz	BANDWIDTH WITH CLOCK RATE OF 737.28 MHz
LP	LP	0 MHz–100 MHz	100 MHz	0 MHz–75 MHz	75 MHz
LP	HP	150 MHz–223 MHz	73 MHz	112.5 MHz–167.25 MHz	54.75 MHz
HP	LP	268.52 MHz–341.52 MHz	73 MHz	201.39 MHz–256.14 MHz	54.75 MHz
HP	HP	391.52 MHz–491.52 MHz	100 MHz	293.64 MHz–368.64 MHz	75 MHz