In burst mode, the decimate-by-2 data are output alternating between low resolution (L, 9-bit) and high resolution (H, 14-bit) output. The burst mode can be configured via SPI register writes independently for channels A, B and channels C, D. The high-resolution output is 14 bits and the number of high- and low-resolution samples is set with two user-programmable counters: one for high resolution (HC) and one for low resolution (LC). There is one counter pair (HC, LC) for channels A, B and one pair for channels C, D. The internal logic checks if the maximum duty cycle is exceeded and, if necessary, resets the counters to default values. Each output cycle starts with a low resolution and the counter values can be reconfigured for the next cycle prior to the start of the next cycle. The number of high-resolution samples is equal to two times the high-resolution count (HC). Similarly, the number of low-resolution samples is equal to two times the low-resolution count (LC).

An example of burst mode with mode 8 is shown in Figure 7-16.

Figure 7-16 Burst Mode

The counter values for high and low resolution can be programmed to:

High-resolution counter (HC): 1 to 2²⁵

Low-resolution counter (LC): 1 to 2²⁸

The output duty cycle limit is shown in Table 7-3.