The ADS58J64 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high-impedance input across a very wide frequency range to the external driving source that enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more constant SFDR performance across input frequencies. The common-mode voltage of the signal inputs is internally biased to 1.3 V using 2-kΩ resistors to allow for ac-coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.275 V) and (VCM – 0.275 V), resulting in a 1.1-V_PP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 1000 MHz.