ZHCSFY7B January   2017  – December 2021 ADS58J64

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Typical Characteristics: 14-Bit Burst Mode
    10. 6.10 Typical Characteristics: Mode 2
    11. 6.11 Typical Characteristics: Mode 0
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Recommended Input Circuit
      3. 7.3.3 Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Features
        1. 7.4.1.1  Numerically Controlled Oscillators (NCOs) and Mixers
        2. 7.4.1.2  Decimation Filter
          1. 7.4.1.2.1 Stage-1 Filter
          2. 7.4.1.2.2 Stage-2 Filter
        3. 7.4.1.3  Mode 0: Decimate-by-4 With IQ Outputs and fS / 4 Mixer
        4. 7.4.1.4  Mode 1: Decimate-by-4 With IQ Outputs and 16-Bit NCO
        5. 7.4.1.5  Mode 2: Decimate-by-4 With Real Output
        6. 7.4.1.6  Mode 3: Decimate-by-2 Real Output With Frequency Shift
        7. 7.4.1.7  Mode 4: Decimate-by-4 With Real Output
        8. 7.4.1.8  Mode 6: Decimate-by-4 With IQ Outputs for up to 110 MHz of IQ Bandwidth
        9. 7.4.1.9  Mode 7: Decimate-by-4 With Real Output and Zero Stuffing
        10. 7.4.1.10 Mode 8: Burst Mode
        11. 7.4.1.11 Trigger Input
        12. 7.4.1.12 Manual Trigger Mode
        13. 7.4.1.13 Auto Trigger Mode
        14. 7.4.1.14 Overrange Indication
    5. 7.5 Programming
      1. 7.5.1 JESD204B Interface
      2. 7.5.2 JESD204B Initial Lane Alignment (ILA)
      3. 7.5.3 JESD204B Frame Assembly
      4. 7.5.4 JESD Output Switch
        1. 7.5.4.1 SerDes Transmitter Interface
        2. 7.5.4.2 SYNCb Interface
        3. 7.5.4.3 Eye Diagram
      5. 7.5.5 Device Configuration
        1. 7.5.5.1 Details of the Serial Interface
          1. 7.5.5.1.1 Register Initialization
        2. 7.5.5.2 Serial Register Write
        3. 7.5.5.3 Serial Read
    6. 7.6 Register Maps
      1. 7.6.1 Register Map
        1. 7.6.1.1 Register Description
          1. 7.6.1.1.1 GLOBAL Page Register Description
            1. 7.6.1.1.1.1 Register 00h (address = 00h) [reset = 0h], GLOBAL Page
            2. 7.6.1.1.1.2 Register 04h (address = 04h) [reset = 0h], GLOBAL Page
            3. 7.6.1.1.1.3 Register 11h (address = 11h) [reset = 0h], GLOBAL Page
            4. 7.6.1.1.1.4 Register 12h (address = 12h) [reset = 0h], GLOBAL Page
            5. 7.6.1.1.1.5 Register 13h (address = 13h) [reset = 0h], GLOBAL Page
          2. 7.6.1.1.2 DIGTOP Page Register Description
            1. 7.6.1.1.2.1  Register 64h (address = 64h) [reset = 0h], DIGTOP Page
            2. 7.6.1.1.2.2  Register 8Dh (address = 8Dh) [reset = 0h], DIGTOP Page
            3. 7.6.1.1.2.3  Register 8Eh (address = 8Eh) [reset = 0h], DIGTOP Page
            4. 7.6.1.1.2.4  Register 8Fh (address = 8Fh) [reset = 0h], DIGTOP Page
            5. 7.6.1.1.2.5  Register 90h (address = 90h) [reset = 0h], DIGTOP Page
            6. 7.6.1.1.2.6  Register 91h (address = 91h) [reset = 0h], DIGTOP Page
            7. 7.6.1.1.2.7  Register ABh (address = ABh) [reset = 0h], DIGTOP Page
            8. 7.6.1.1.2.8  Register ACh (address = ACh) [reset = 0h], DIGTOP Page
            9. 7.6.1.1.2.9  Register ADh (address = ADh) [reset = 0h], DIGTOP Page
            10. 7.6.1.1.2.10 Register AEh (address = AEh) [reset = 0h], DIGTOP Page
            11. 7.6.1.1.2.11 Register B7h (address = B7h) [reset = 0h], DIGTOP Page
          3. 7.6.1.1.3 ANALOG Page Register Description
            1. 7.6.1.1.3.1  Register 6Ah (address = 6Ah) [reset = 0h], ANALOG Page
            2. 7.6.1.1.3.2  Register 6Fh (address = 6Fh) [reset = 0h], ANALOG Page
            3. 7.6.1.1.3.3  Register 71h (address = 71h) [reset = 0h], ANALOG Page
            4. 7.6.1.1.3.4  Register 72h (address = 72h) [reset = 0h], ANALOG Page
            5. 7.6.1.1.3.5  Register 93h (address = 93h) [reset = 0h], ANALOG Page
            6. 7.6.1.1.3.6  Register 94h (address = 94h) [reset = 0h], ANALOG Page
            7. 7.6.1.1.3.7  Register 9Bh (address = 9Bh) [reset = 0h], ANALOG Page
            8. 7.6.1.1.3.8  Register 9Dh (address = 9Dh) [reset = 0h], ANALOG Page
            9. 7.6.1.1.3.9  Register 9Eh (address = 9Eh) [reset = 0h], ANALOG Page
            10. 7.6.1.1.3.10 Register 9Fh (address = 9Fh) [reset = 0h], ANALOG Page
            11. 7.6.1.1.3.11 Register AFh (address = AFh) [reset = 0h], ANALOG Page
          4. 7.6.1.1.4 SERDES_XX Page Register Description
            1. 7.6.1.1.4.1  Register 20h (address = 20h) [reset = 0h], SERDES_XX Page
            2. 7.6.1.1.4.2  Register 21h (address = 21h) [reset = 0h], SERDES_XX Page
            3. 7.6.1.1.4.3  Register 22h (address = 22h) [reset = 0h], SERDES_XX Page
            4. 7.6.1.1.4.4  Register 23h (address = 23h) [reset = 0h], SERDES_XX Page
            5. 7.6.1.1.4.5  Register 25h (address = 25h) [reset = 0h], SERDES_XX Page
            6. 7.6.1.1.4.6  Register 26h (address = 26h) [reset = 0h], SERDES_XX Page
            7. 7.6.1.1.4.7  Register 28h (address = 28h) [reset = 0h], SERDES_XX Page
            8. 7.6.1.1.4.8  Register 2Dh (address = 2Dh) [reset = 0h], SERDES_XX Page
            9. 7.6.1.1.4.9  Register 36h (address = 36h) [reset = 0h], SERDES_XX Page
            10. 7.6.1.1.4.10 Register 37h (address = 37h) [reset = 0h], SERDES_XX Page
            11. 7.6.1.1.4.11 Register 39h (address = 39h) [reset = 0h], SERDES_XX Page
            12. 7.6.1.1.4.12 Register 3Ah (address = 3Ah) [reset = 0h], SERDES_XX Page
            13. 7.6.1.1.4.13 Register 3Bh (address = 3Bh) [reset = 0h], SERDES_XX Page
            14. 7.6.1.1.4.14 Register 3Ch (address = 3Ch) [reset = 0h], SERDES_XX Page
            15. 7.6.1.1.4.15 Register 3Dh (address = 3Dh) [reset = 0h], SERDES_XX Page
            16. 7.6.1.1.4.16 Register 3Eh (address = 3Eh) [reset = 0h], SERDES_XX Page
            17. 7.6.1.1.4.17 Register 3Fh (address = 3Fh) [reset = 0h], SERDES_XX Page
            18. 7.6.1.1.4.18 Register 40h (address = 40h) [reset = 0h], SERDES_XX Page
            19. 7.6.1.1.4.19 Register 41h (address = 41h) [reset = 0h], SERDES_XX Page
            20. 7.6.1.1.4.20 Register 42h (address = 42h) [reset = 0h], SERDES_XX Page
          5. 7.6.1.1.5 CHX Page Register Description
            1. 7.6.1.1.5.1 Register 26h (address = 26h) [reset = 0h], CHX Page
            2. 7.6.1.1.5.2 Register 27h (address = 27h) [reset = 0h], CHX Page
            3. 7.6.1.1.5.3 Register 2Dh (address = 2Dh) [reset = 0h], CHX Page
            4. 7.6.1.1.5.4 Register 78h (address = 78h) [reset = 0h], CHX Page
            5. 7.6.1.1.5.5 Register 7Ah (address = 7Ah) [reset = 0h], CHX Page
            6. 7.6.1.1.5.6 Register 7Bh (address = 7Bh) [reset = 0h], CHX Page
            7. 7.6.1.1.5.7 Register 7Eh (address = 7Eh) [reset = 3h], CHX Page
          6. 7.6.1.1.6 ADCXX Page Register Description
            1. 7.6.1.1.6.1 Register 07h (address = 07h) [reset = FFh], ADCXX Page
            2. 7.6.1.1.6.2 Register 08h (address = 08h) [reset = 0h], ADCXX Page
            3. 7.6.1.1.6.3 Register D5h (address = D5h) [reset = 0h], ADCXX Page
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-Up Sequence
      2. 8.1.2 Hardware Reset
      3. 8.1.3 Frequency Planning
      4. 8.1.4 SNR and Clock Jitter
      5. 8.1.5 ADC Test Pattern
        1. 8.1.5.1 ADC Section
        2. 8.1.5.2 Transport Layer Pattern
        3. 8.1.5.3 Link Layer Pattern
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.3 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

  • L is the number of lanes per link
  • M is the number of converters per device
  • F is the number of octets per frame clock period
  • S is the number of samples per frame

Table 7-4 lists the available JESD204B formats and valid ranges for the ADS58J64. The ranges are limited by the SerDes line rate and the maximum ADC sample frequency.

Table 7-4 Available JESD204B Formats and Valid Ranges for the ADS58J64
LMFSOPERATING MODEDIGITAL MODEOUTPUT FORMATJESD MODEJESD PLL MODEMAX ADC OUTPUT
RATE (MSPS)		MAX fSerDes
(Gbps)		JESD PLL REGISTER CONFIGURATION
48410, 12x decimationComplex40x40x25010.0—
44212, 42x decimationReal20x20x2505.0CTRL_SER_MODE = 1,
SerDes_MODE = 1
24412, 42x decimationReal40x40x25010.0—
484164x decimationComplex40x20x1255.0—
288164x decimationComplex80x40x12510.0CTRL_SER_MODE = 1,
SerDes_MODE = 3
442172x decimation with 0-padReal20x40x50010.0—
44213, 8Burst modeReal20x40x50010.0—

The detailed frame assembly for various LMFS settings are shown in Table 7-5 and Table 7-6.

Table 7-5 Detailed Frame Assembly for Four-Lane Modes (Mode 0, 1, 3, 6, 7, and 8)
OUTPUT LANELMFS = 4841LMFS = 4421LMFS = 4421 (0-Pad)
DAAI0[15:8]AI0[7:0]AQ0[15:8]AQ0[7:0]A0[15:8]A0[7:0]A1[15:8]A1[7:0]A0[15:8]A0[7:0]0000 00000000 0000
DBBI0[15:8]BI0[7:0]BQ0[15:8]BQ0[7:0]B0[15:8]B0[7:0]B1[15:8]B1[7:0]B0[15:8]B0[7:0]0000 00000000 0000
DCCI0[15:8]CI0[7:0]CQ0[15:8]CQ0[7:0]C0[15:8]C0[7:0]C1[15:8]C1[7:0]C0[15:8]C0[7:0]0000 00000000 0000
DDDI0[15:8]DI0[7:0]DQ0[15:8]DQ0[7:0]D0[15:8]D0[7:0]D1[15:8]D1[7:0]D0[15:8]D0[7:0]0000 00000000 0000
Table 7-6 Detailed Frame Assembly for Two-Lane Modes (Mode 2 and 4)
OUTPUT LANELMFS = 2441LMFS = 2881
DBA0[15:8]A0[7:0]B0[15:8]B0[7:0]AI0[15:8]AI0[7:0]AQ0[15:8]AQ0[7:0]BI0[15:8]BI0[7:0]BQ0[15:8]BQ0[7:0]
DCC0[15:8]C0[7:0]D0[15:8]D0[7:0]CI0[15:8]CI0[7:0]CQ0[15:8]CQ0[7:0]DI0[15:8]DI0[7:0]DQ0[15:8]DQ0[7:0]
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