The ADS58J64 uses an architecture where the ADCs are 2x interleaved followed by a digital decimation by 2. The 2x interleaved and decimation architecture comes with a unique advantage of improved linearity resulting from frequency planning. Frequency planning refers to choosing the clock frequency and signal band appropriately such that the harmonic distortion components, resulting from the analog front-end (LNA, PGA), can be made to fall outside the decimation filter pass band. In absence of the 2x interleave and decimation architecture, these components alias back in band and limit the performance of the signal chain. For example, for f_CLK = 983.04 MHz and f_IN = 184.32 MHz:

Second-order harmonic distortion (HD2) = 2 × 184.32 = 368.64 MHz

Pass band of the 2x decimation filter = 0 MHz to 245.76 MHz (0 to f_CLK / 4)

The second-order harmonic performance improves by the stop-band attenuation of the filter (approximately 40 dBc) because the second-order harmonic frequency is outside the pass band of the decimation filter.

Figure 8-2 shows the harmonic components (HD2–HD5) that fall in the decimation pass band for the input clock rate (f_CLK) of the 983.04-MHz and 100-MHz signal band around the center frequency of 184.32 MHz.

f_CLK = 983.04 MHz, signal band = 134.32 MHz to 234.32 MHz

Figure 8-2 In-Band Harmonics for a Frequency Planned System

As shown in Figure 8-2, both HD2 and HD3 are completely out of band. HD4 and HD5 fall in the decimation pass band for some frequencies of the input signal band.

Through proper frequency planning, the specifications of the ADC antialias filter can be relaxed.